diff options
Diffstat (limited to 'include/pmu_ethosu.h')
| -rw-r--r-- | include/pmu_ethosu.h | 86 |
1 files changed, 21 insertions, 65 deletions
diff --git a/include/pmu_ethosu.h b/include/pmu_ethosu.h index a344146..ceefda8 100644 --- a/include/pmu_ethosu.h +++ b/include/pmu_ethosu.h @@ -139,48 +139,36 @@ enum ethosu_pmu_event_type /** * \brief Enable the PMU */ -void ETHOSU_PMU_Enable_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_Enable(void) ETHOSU_PMU_Enable_v2(ðosu_drv) +void ETHOSU_PMU_Enable(struct ethosu_driver *drv); /** * \brief Disable the PMU */ -void ETHOSU_PMU_Disable_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_Disable(void) ETHOSU_PMU_Disable_v2(ðosu_drv) +void ETHOSU_PMU_Disable(struct ethosu_driver *drv); /** * \brief Set event to count for PMU eventer counter * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure * \param [in] type Event to count */ -void ETHOSU_PMU_Set_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type); - -#define ETHOSU_PMU_Set_EVTYPER(num, type) ETHOSU_PMU_Set_EVTYPER_v2(ðosu_drv, num, type) +void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type); /** * \brief Get event to count for PMU eventer counter * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) to configure * \return type Event to count */ -enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER_v2(struct ethosu_driver *drv, uint32_t num); - -#define ETHOSU_PMU_Get_EVTYPER(num) ETHOSU_PMU_Get_EVTYPER_v2(ðosu_drv, num) +enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num); /** * \brief Reset cycle counter */ -void ETHOSU_PMU_CYCCNT_Reset_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_CYCCNT_Reset(void) ETHOSU_PMU_CYCCNT_Reset_v2(ðosu_drv) +void ETHOSU_PMU_CYCCNT_Reset(struct ethosu_driver *drv); /** * \brief Reset all event counters */ -void ETHOSU_PMU_EVCNTR_ALL_Reset_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_EVCNTR_ALL_Reset(void) ETHOSU_PMU_EVCNTR_ALL_Reset_v2(ðosu_drv) +void ETHOSU_PMU_EVCNTR_ALL_Reset(struct ethosu_driver *drv); /** * \brief Enable counters @@ -189,9 +177,7 @@ void ETHOSU_PMU_EVCNTR_ALL_Reset_v2(struct ethosu_driver *drv); * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) * - cycle counter (bit 31) */ -void ETHOSU_PMU_CNTR_Enable_v2(struct ethosu_driver *drv, uint32_t mask); - -#define ETHOSU_PMU_CNTR_Enable(mask) ETHOSU_PMU_CNTR_Enable_v2(ðosu_drv, mask) +void ETHOSU_PMU_CNTR_Enable(struct ethosu_driver *drv, uint32_t mask); /** * \brief Disable counters @@ -200,9 +186,7 @@ void ETHOSU_PMU_CNTR_Enable_v2(struct ethosu_driver *drv, uint32_t mask); * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) * - cycle counter (bit 31) */ -void ETHOSU_PMU_CNTR_Disable_v2(struct ethosu_driver *drv, uint32_t mask); - -#define ETHOSU_PMU_CNTR_Disable(mask) ETHOSU_PMU_CNTR_Disable_v2(ðosu_drv, mask) +void ETHOSU_PMU_CNTR_Disable(struct ethosu_driver *drv, uint32_t mask); /** * \brief Determine counters activation @@ -214,9 +198,7 @@ void ETHOSU_PMU_CNTR_Disable_v2(struct ethosu_driver *drv, uint32_t mask); * - cycle counter activate (bit 31) * \note ETHOSU specific. Usage breaks CMSIS complience */ -uint32_t ETHOSU_PMU_CNTR_Status_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_CNTR_Status(void) ETHOSU_PMU_CNTR_Status_v2(ðosu_drv) +uint32_t ETHOSU_PMU_CNTR_Status(struct ethosu_driver *drv); /** * \brief Read cycle counter (64 bit) @@ -227,9 +209,7 @@ uint32_t ETHOSU_PMU_CNTR_Status_v2(struct ethosu_driver *drv); * is not greater than the former, it means overflow of LSW without * incrementing MSW has occurred, in which case the former value is used. */ -uint64_t ETHOSU_PMU_Get_CCNTR_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_Get_CCNTR(void) ETHOSU_PMU_Get_CCNTR_v2(ðosu_drv) +uint64_t ETHOSU_PMU_Get_CCNTR(struct ethosu_driver *drv); /** * \brief Set cycle counter (64 bit) @@ -238,18 +218,14 @@ uint64_t ETHOSU_PMU_Get_CCNTR_v2(struct ethosu_driver *drv); * To work-around raciness, counter is temporary disabled if enabled. * \note ETHOSU specific. Usage breaks CMSIS complience */ -void ETHOSU_PMU_Set_CCNTR_v2(struct ethosu_driver *drv, uint64_t val); - -#define ETHOSU_PMU_Set_CCNTR(val) ETHOSU_PMU_Set_CCNTR_v2(ðosu_drv, val) +void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val); /** * \brief Read event counter * \param [in] num Event counter (0-ETHOSU_PMU_NCOUNTERS) * \return Event count */ -uint32_t ETHOSU_PMU_Get_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num); - -#define ETHOSU_PMU_Get_EVCNTR(num) ETHOSU_PMU_Get_EVCNTR_v2(ðosu_drv, num) +uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num); /** * \brief Set event counter value @@ -257,9 +233,7 @@ uint32_t ETHOSU_PMU_Get_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num); * \param [in] val Conter value * \note ETHOSU specific. Usage breaks CMSIS complience */ -void ETHOSU_PMU_Set_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num, uint32_t val); - -#define ETHOSU_PMU_Set_EVCNTR(num, val) ETHOSU_PMU_Set_EVCNTR_v2(ðosu_drv, num, val) +void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val); /** * \brief Read counter overflow status @@ -267,9 +241,7 @@ void ETHOSU_PMU_Set_EVCNTR_v2(struct ethosu_driver *drv, uint32_t num, uint32_t * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS)) * - cycle counter (bit 31) */ -uint32_t ETHOSU_PMU_Get_CNTR_OVS_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_Get_CNTR_OVS(void) ETHOSU_PMU_Get_CNTR_OVS_v2(ðosu_drv) +uint32_t ETHOSU_PMU_Get_CNTR_OVS(struct ethosu_driver *drv); /** * \brief Clear counter overflow status @@ -278,9 +250,7 @@ uint32_t ETHOSU_PMU_Get_CNTR_OVS_v2(struct ethosu_driver *drv); * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) * - cycle counter (bit 31) */ -void ETHOSU_PMU_Set_CNTR_OVS_v2(struct ethosu_driver *drv, uint32_t mask); - -#define ETHOSU_PMU_Set_CNTR_OVS(mask) ETHOSU_PMU_Set_CNTR_OVS_v2(ðosu_drv, mask) +void ETHOSU_PMU_Set_CNTR_OVS(struct ethosu_driver *drv, uint32_t mask); /** * \brief Enable counter overflow interrupt request @@ -289,9 +259,7 @@ void ETHOSU_PMU_Set_CNTR_OVS_v2(struct ethosu_driver *drv, uint32_t mask); * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) * - cycle counter (bit 31) */ -void ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(struct ethosu_driver *drv, uint32_t mask); - -#define ETHOSU_PMU_Set_CNTR_IRQ_Enable(mask) ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(ðosu_drv, mask) +void ETHOSU_PMU_Set_CNTR_IRQ_Enable(struct ethosu_driver *drv, uint32_t mask); /** * \brief Disable counter overflow interrupt request @@ -300,9 +268,7 @@ void ETHOSU_PMU_Set_CNTR_IRQ_Enable_v2(struct ethosu_driver *drv, uint32_t mask) * - event counters (bit 0-ETHOSU_PMU_NCOUNTERS) * - cycle counter (bit 31) */ -void ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(struct ethosu_driver *drv, uint32_t mask); - -#define ETHOSU_PMU_Set_CNTR_IRQ_Disable(mask) ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(ðosu_drv, mask) +void ETHOSU_PMU_Set_CNTR_IRQ_Disable(struct ethosu_driver *drv, uint32_t mask); /** * \brief Get counters overflow interrupt request stiinings @@ -312,9 +278,7 @@ void ETHOSU_PMU_Set_CNTR_IRQ_Disable_v2(struct ethosu_driver *drv, uint32_t mask * - cycle counter (bit 31) * \note ETHOSU specific. Usage breaks CMSIS compliance */ -uint32_t ETHOSU_PMU_Get_IRQ_Enable_v2(struct ethosu_driver *drv); - -#define ETHOSU_PMU_Get_IRQ_Enable(void) ETHOSU_PMU_Get_IRQ_Enable_v2(ðosu_drv) +uint32_t ETHOSU_PMU_Get_IRQ_Enable(struct ethosu_driver *drv); /** * \brief Software increment event counter @@ -323,29 +287,21 @@ uint32_t ETHOSU_PMU_Get_IRQ_Enable_v2(struct ethosu_driver *drv); * - cycle counter (bit 31) * \note Software increment bits for one or more event counters. */ -void ETHOSU_PMU_CNTR_Increment_v2(struct ethosu_driver *drv, uint32_t mask); - -#define ETHOSU_PMU_CNTR_Increment(mask) ETHOSU_PMU_CNTR_Increment_v2(ðosu_drv, mask) +void ETHOSU_PMU_CNTR_Increment(struct ethosu_driver *drv, uint32_t mask); /** * \brief Set start event number for the cycle counter * \param [in] start_event Event to trigger start of the cycle counter * \note Sets the event number that starts the cycle counter. */ -void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event); - -#define ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(start_event) \ - ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event_v2(ðosu_drv, start_event) +void ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type start_event); /** * \brief Set stop event number for the cycle counter * \param [in] stop_event Event number * \note Sets the event number that stops the cycle counter. */ -void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event); - -#define ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(stop_event) \ - ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event_v2(ðosu_drv, stop_event) +void ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(struct ethosu_driver *drv, enum ethosu_pmu_event_type stop_event); #ifdef __cplusplus } |