Optimizations21.05-rc3

Removing the ASSERT() makro using assert() instead. assert() is better
controlled with the NDEBUG define.

Using uintptr_t instead of uint32_t * for the NPU base address. This
saves a division by 4 in the register read and write functions.

Change-Id: I65a91fe35dc63666e50bdf7a756ad15b56dc66e9

5 files changed, 20 insertions, 26 deletions

diff --git a/include/ethosu_device.h b/include/ethosu_device.h
index 35f7924..0221ad1 100644
--- a/include/ethosu_device.h
+++ b/include/ethosu_device.h
@@ -56,7 +56,7 @@ enum ethosu_error_codes
 
 struct ethosu_device
 {
-    volatile uint32_t *base_address;
+    volatile uintptr_t base_address;
     uint32_t proto;
     uint32_t pmcr;
     uint32_t pmccntr[2];
diff --git a/src/ethosu_common.h b/src/ethosu_common.h
index 30f07be..bf3aff0 100644
--- a/src/ethosu_common.h
+++ b/src/ethosu_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -105,12 +105,6 @@
 #define LOG_DEBUG(format, ...)
 #endif
 
-#if defined(ASSERT_DISABLE)
-#define ASSERT(args)
-#else
-#define ASSERT(args) assert(args)
-#endif
-
 #define UNUSED(x) ((void)x)
 
 #define VER_STR(X) VNUM_STR(X)
diff --git a/src/ethosu_device.c b/src/ethosu_device.c
index 1667325..c7cded9 100644
--- a/src/ethosu_device.c
+++ b/src/ethosu_device.c
@@ -40,7 +40,7 @@ enum ethosu_error_codes ethosu_dev_init(struct ethosu_device *dev,
                                         uint32_t privilege_enable)
 {
 #if !defined(ARM_NPU_STUB)
-    dev->base_address = (volatile uint32_t *)base_address;
+    dev->base_address = (volatile uintptr_t)base_address;
     dev->secure       = secure_enable;
     dev->privileged   = privilege_enable;
 
@@ -105,10 +105,10 @@ enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev,
     enum ethosu_error_codes ret_code = ETHOSU_SUCCESS;
 
 #if !defined(ARM_NPU_STUB)
-    ASSERT(num_base_addr <= ETHOSU_DRIVER_BASEP_INDEXES);
+    assert(num_base_addr <= ETHOSU_DRIVER_BASEP_INDEXES);
 
     uint64_t qbase = (uintptr_t)cmd_stream_ptr + BASE_POINTER_OFFSET;
-    ASSERT(qbase <= ADDRESS_MASK);
+    assert(qbase <= ADDRESS_MASK);
     LOG_DEBUG("QBASE=0x%016llx, QSIZE=%u, base_pointer_offset=0x%08x\n", qbase, cms_length, BASE_POINTER_OFFSET);
     ethosu_write_reg(dev, NPU_REG_QBASE0, qbase & 0xffffffff);
     ethosu_write_reg(dev, NPU_REG_QBASE1, qbase >> 32);
@@ -117,7 +117,7 @@ enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev,
     for (int i = 0; i < num_base_addr; i++)
     {
         uint64_t addr = base_addr[i] + BASE_POINTER_OFFSET;
-        ASSERT(addr <= ADDRESS_MASK);
+        assert(addr <= ADDRESS_MASK);
         LOG_DEBUG("BASEP%d=0x%016llx\n", i, addr);
         ethosu_write_reg(dev, NPU_REG_BASEP0 + (2 * i) * BASEP_OFFSET, addr & 0xffffffff);
         ethosu_write_reg(dev, NPU_REG_BASEP0 + (2 * i + 1) * BASEP_OFFSET, addr >> 32);
@@ -130,7 +130,7 @@ enum ethosu_error_codes ethosu_run_command_stream(struct ethosu_device *dev,
     stream_length = cms_length;
     UNUSED(cmd_stream_ptr);
     UNUSED(base_addr);
-    ASSERT(num_base_addr < ETHOSU_DRIVER_BASEP_INDEXES);
+    assert(num_base_addr < ETHOSU_DRIVER_BASEP_INDEXES);
 #if defined(NDEBUG)
     UNUSED(num_base_addr);
 #endif
@@ -259,7 +259,7 @@ enum ethosu_error_codes ethosu_read_apb_reg(struct ethosu_device *dev,
 #if !defined(ARM_NPU_STUB)
     uint32_t address = start_address;
 
-    ASSERT((start_address + num_reg) < ID_REGISTERS_SIZE);
+    assert((start_address + num_reg) < ID_REGISTERS_SIZE);
 
     for (int i = 0; i < num_reg; i++)
     {
@@ -564,10 +564,10 @@ enum ethosu_error_codes ethosu_set_clock_and_power(struct ethosu_device *dev,
 uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address)
 {
 #if !defined(ARM_NPU_STUB)
-    ASSERT(dev->base_address != 0);
-    ASSERT(address % 4 == 0);
+    assert(dev->base_address != 0);
+    assert(address % 4 == 0);
 
-    volatile uint32_t *reg = dev->base_address + address / sizeof(uint32_t);
+    volatile uint32_t *reg = dev->base_address + address;
     return *reg;
 #else
     UNUSED(dev);
@@ -580,10 +580,10 @@ uint32_t ethosu_read_reg(struct ethosu_device *dev, uint32_t address)
 void ethosu_write_reg(struct ethosu_device *dev, uint32_t address, uint32_t value)
 {
 #if !defined(ARM_NPU_STUB)
-    ASSERT(dev->base_address != 0);
-    ASSERT(address % 4 == 0);
+    assert(dev->base_address != 0);
+    assert(address % 4 == 0);
 
-    volatile uint32_t *reg = dev->base_address + address / sizeof(uint32_t);
+    volatile uint32_t *reg = dev->base_address + address;
     *reg                   = value;
 #else
     UNUSED(dev);
diff --git a/src/ethosu_driver.c b/src/ethosu_driver.c
index 5910fa4..4c1b100 100644
--- a/src/ethosu_driver.c
+++ b/src/ethosu_driver.c
@@ -229,7 +229,7 @@ void __attribute__((weak)) ethosu_irq_handler(struct ethosu_driver *drv)
 
     // Verify that interrupt has been raised
     (void)ethosu_is_irq_raised(&drv->dev, &irq_raised);
-    ASSERT(irq_raised == 1);
+    assert(irq_raised == 1);
     drv->irq_triggered = true;
 
     // Clear interrupt
@@ -237,7 +237,7 @@ void __attribute__((weak)) ethosu_irq_handler(struct ethosu_driver *drv)
 
     // Verify that interrupt has been successfully cleared
     (void)ethosu_is_irq_raised(&drv->dev, &irq_raised);
-    ASSERT(irq_raised == 0);
+    assert(irq_raised == 0);
 
     if (ethosu_status_has_error(&drv->dev))
     {
diff --git a/src/ethosu_pmu.c b/src/ethosu_pmu.c
index a88dfb6..5872d18 100644
--- a/src/ethosu_pmu.c
+++ b/src/ethosu_pmu.c
@@ -106,7 +106,7 @@ void ETHOSU_PMU_Disable(struct ethosu_driver *drv)
 
 void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu_pmu_event_type type)
 {
-    ASSERT(num < ETHOSU_PMU_NCOUNTERS);
+    assert(num < ETHOSU_PMU_NCOUNTERS);
     uint32_t val = pmu_event_value(type);
     LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val);
     ethosu_write_reg_shadow(&drv->dev, NPU_REG_PMEVTYPER(num), val, &drv->dev.pmu_evtypr[num]);
@@ -114,7 +114,7 @@ void ETHOSU_PMU_Set_EVTYPER(struct ethosu_driver *drv, uint32_t num, enum ethosu
 
 enum ethosu_pmu_event_type ETHOSU_PMU_Get_EVTYPER(struct ethosu_driver *drv, uint32_t num)
 {
-    ASSERT(num < ETHOSU_PMU_NCOUNTERS);
+    assert(num < ETHOSU_PMU_NCOUNTERS);
     uint32_t val                    = drv->dev.pmu_evtypr[num];
     enum ethosu_pmu_event_type type = pmu_event_type(val);
     LOG_DEBUG("%s: num=%u, type=%d, val=%u\n", __FUNCTION__, num, type, val);
@@ -208,7 +208,7 @@ void ETHOSU_PMU_Set_CCNTR(struct ethosu_driver *drv, uint64_t val)
 
 uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num)
 {
-    ASSERT(num < ETHOSU_PMU_NCOUNTERS);
+    assert(num < ETHOSU_PMU_NCOUNTERS);
     uint32_t val = ethosu_read_reg(&drv->dev, NPU_REG_PMEVCNTR(num));
     LOG_DEBUG("%s: num=%u, val=%u, shadow=%u\n", __FUNCTION__, num, val, drv->dev.pmu_evcntr[num]);
 
@@ -226,7 +226,7 @@ uint32_t ETHOSU_PMU_Get_EVCNTR(struct ethosu_driver *drv, uint32_t num)
 
 void ETHOSU_PMU_Set_EVCNTR(struct ethosu_driver *drv, uint32_t num, uint32_t val)
 {
-    ASSERT(num < ETHOSU_PMU_NCOUNTERS);
+    assert(num < ETHOSU_PMU_NCOUNTERS);
     LOG_DEBUG("%s: num=%u, val=%u\n", __FUNCTION__, num, val);
     ethosu_write_reg(&drv->dev, NPU_REG_PMEVCNTR(num), val);
 }