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2024-02-22IVGCVSW-7854 Remove/rewrite asserts in the backends unit tests.Colm Donelan
* Replace calls to ARMNN_ASSERT with DOCTEST CHECK. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I8904d169b2099d57a344e319b2f14cf5d8392ae8
2024-02-21IVGCVSW-7854 Remove/rewrite asserts in the backends.Colm Donelan
* Identify usages of ARMNN_ASSERT that should be proper exceptions. * Change ARMNN_ASSERT in Doctests to CHECK. * Verify any remaining assertions are reasonable. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ifd1f2a5a4bb60135e8654305035ec70e09c4dc2d
2024-02-14Minor adjustment to the commit for MLCE-1165Tracy Narine
* Rewrote constexpr check to avoid a compile error Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: I09a61314b1b4a5aa1e2baa52711f470802f04131
2024-02-13MLCE-1165 Model failing to load when pad is folded into Conv2dTracy Narine
* Skipping the optimization which folds pad and conv2d together for a specific case: 1x1 filter and padding size >= filter size Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: I46944e9f736df1ff60469b2d2852e1bba01ab8cd
2024-02-09IVGCVSW-7569 GpuFsa Op: Add Reshape OperatorDeclan-ARM
* Add Reshape EndToEnd tests to all backends Signed-off-by: Declan-ARM <decmce01@arm.com> Change-Id: Ic6d07ba8de0cf3271ed0e4c6d604e070ccb968e3
2024-02-09IVGCVSW-8275 GpuFsa Op: Add Activation functions availableTeresa Charlin
* Currently Sigmoid and TanH Functions are implemented. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: If9483be9201dfe47b86acc41ec7932725ac2e39e
2024-02-08IVGCVSW-7624 GpuFsa Op: Add Softmax operatorJohn Mcloughlin
* Added softmax operator support * Added test cases Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: I51d530b110c4cb812f5aab31ad1ee4022d81d19e
2024-02-08IVGCVSW-8276 GpuFsa Op: Add MatMulTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib95eb0fd71106e684cb7652917b8de9f0ac73f9c
2024-02-08IVGCVSW-7570 GpuFsa Op: Add ElemenWiseBinary Operators availableTeresa Charlin
* Refactor to generalize * Add MUL Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I2ee273d50d3a8b114b5a41abc8ee7585b15e3308
2024-02-08Add and tidy up activation and elementwise binary end to end testsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I9714c4c57e923ac775dcde2951de07cea35c40ee
2024-02-08IVGCVSW-7625 GpuFsa Op: Add Resize/Scale operatorTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I695ef452d004ed7b606020037cad681ef1fc80c3
2024-02-07IVGCVSW-7622 GpuFsa Op: Add Cast operatorTracy Narine
* Added cast operator support Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: Ie12cb1559a7a059ff35e1c395bc77243499243cd
2024-02-07IVGCVSW-7623: GpuFsa Op: Add Pool2d operatorTeresa Charlin
* Add Pool2d EndToEnd tests to all backends * Add utility functions for the attributes in a separate file * Remove some unnecessary includes Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0f82ebbf7b3301c6368462fb4fb4d4d02b246fc6
2024-02-01Removing unnecessary includes from GpuFsa operators.Colm Donelan
Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I3d089e7f1b75596501130d3ece3a94dd326cc27e
2024-01-31IVGCVSW-7568 Implement Sub ElementwiseBinary operator GpuFsaJohn Mcloughlin
* Added support for Gpu Sub operator * Added unit tests Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: I1efaa485772a3716e3781566843bd50bd9bab811
2024-01-30IVGCVSW-7550 GpuFsa Op: Add ElementWiseBinary Operator ADDTracy Narine
* Adding support for Gpu Add operator * Added tests for layer support, end to end and optimization Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: Ie9328d269c5c0ff60a7e10133b728ac9265033af
2024-01-26IVGCVSW-7571 GpuFsa Op: Add Depthwise Conv2dTianle Cheng
* Added DepthwiseConv2d support for GpuFsa backend. * Updated DepthwiseConv2d End-to-End test Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I646839980d138ae235a00990c97c6e66a4418a5e
2024-01-23IVGCVSW-7628 Update GpuFsa to use ACLs latest fixesOrlaith Monahan
* Updates to the existing GpuFsa backend to incorporate patch: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10990 * Update the ACL pin to include the patch with the fixes Change-Id: I08d111265f4617657ee7f20249aeb111f64ba7a9 Signed-off-by: David Monahan <david.monahan@arm.com>
2024-01-23Minor fixes related to the LeakyRelu Activation support commit (IVGCVSW-7344)Tracy Narine
* Using the tosa defines from the serialization library to avoid compile errors in other backends * Fixing a bug in the version compat macro Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: Ie4ee80666c6f8033bb72e0e6cb8ca5ef41933990
2024-01-22IVGCVSW-7165 - PreCompiledWorkload and Conv2d Integration work for GpuFsaDavid Monahan
* Add PreCompiledWorkload implementation for GpuFsa * Add ConstantWorkload implementation for GpuFsa * Add Input/Output workloads for GpuFsa * Added CopyMemGeneric workload for GpuFsa * Separate creation and validation of sketch tensors into seperate functions Signed-off-by: Kevin May <kevin.may@arm.com> Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ie7299a4c61073b5ca03d9f8681458869ef7ce743
2024-01-18Bugfix: Remove implicit sign conversion causing -Werror=sign-conversionFrancis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: If2d5005889b8b0011e4592b46276367798556751
2024-01-17IVGCVSW-7344 Add LeakyRelu Activation support to TOSA Reference BackendTracy Narine
* Adding a one to many FP32 tosa mapping for Leaky Relu * Added a few utilities that are needed * Added new tests Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: If1d7c57a523961581777a244416a7346a9310803
2024-01-03IVGCVSW-8118 Added Two-Layer and Three-Layer Maxpool2d EndToEnd tests.Tianle Cheng
Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I4d04fef5ce97901cd687e29adf86b18cb54a5d9a
2024-01-02Fix for Resize with align corners = true creates a memory leak when using ↵Teresa Charlin
valgrind * Add end to end unit test to CpuRef, CpuAcc and GpuAcc backends Resolves: IVGCVSW-8193 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I7be226f084ec814ac72c2c9b3c47c07b3baf0aa5
2023-12-21Add Quantize Support to TOSA Ref BackendTeresa Charlin
* Adding a one to many tosa mapping for Quantize * Added tests * Resolves IVGCVSW-7175 Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ia0852fefb618b4a29c2601b9de8b6b2731229801
2023-12-21Remove the 2 resize tests with align corners from RefEndToEnd.Teresa Charlin
* Relates to IVGCVSW-8193 and IVGCVSW-7346 Change-Id: Ieccee93672a5c73297c4ce69d1eaec588e858df0 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I44df03acd348532a54b66541d91610d382a222b7
2023-12-20IVGCVSW-7830 Remove Reshape where possibleMike Kelly
* Remove reshape on ClBackend * Remove unnecessary restriction on NeonBackend remove Reshape Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I79940c9f8609d19b79f2fbe55225ffc8f0d90c25
2023-12-15IVGCVSW-8113 Update EndToEnd tests and TosaReference support for MaximumTianle Cheng
* Added ElementwiseBinary EndToEnd tests with inputs of the same shape to avoid Reshape * Added Slice EndToEnd tests with 4D tensors * Added TosaReference support for Maximum and TosaRefEndToEnd tests Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I4fa24435a75559e00b110d0e542b4f2bf07b21b4
2023-12-14Fix incorrect Split Tosa Ref outputs checkKevin May
* Resolves IVGCVSW-7918 Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Idd15ce139f55895957378f9a9d1471e3e48989bb
2023-12-14Add Split support to TOSA Reference BackendKevin May
* Resolves IVGCVSW-7918 Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Ic2afaa55f7ee88ce4c9b8ea696eef5f28663f8c6
2023-12-13Add Resize Nearest Neighbour support to TOSA Reference BackendTeresa Charlin
* Add support for quantized data in TosaRefPreCompiledWorkloadGetOutput. * Remove extra includes from all TOSA operators headers. * Added positive and negative unit tests for resize. * Resolves: IVGCVSW-7346 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib6e30d018a7a1bf26b380fc794560aae108b26c3
2023-12-11IVGCVSW-8157 - Nightly Failure FixDavid Monahan
* Added in missing include MemoryGroup.h Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I2a5f4f25ec8cdd63d90399c042d46e26b3e2a364
2023-12-07IVGCVSW-8157 - Rebase existing GpuFsa patches to 23.11David Monahan
Squashed commit of the following: IVGCVSW-7159 Add GpuFsa backend skeleton IVGCVSW-7380 Update the GpuFsa Skeleton to build and load ACL IVGCVSW-7381 Add IsLayerSupported implementation to GpuFsa backend IVGCVSW-7382 Implementation of Conv2d within GpuFsa Signed-off-by: James Conroy <james.conroy@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Id23d9ee598535de7b38a99ca223cdf0ad2102cef
2023-12-05IVGCVSW-8159 Fixed issues building with NDK r26Mike Kelly
* The compiler shipped with NDK r26 has stricter rules around certain warnings and deprecation notices. * Fixed warnings for unqualified call to 'std::move' * Fixed error where the half values weren't being cast to a float when calling 'std::nan' * Removed unnecessary subtensor unit tests for neon Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I4ceb46e55ff5f2a754452e3a43de2188d58bf927
2023-11-10IVGCVSW-7835 Add ReverseV2 CL and Neon WorkloadsTianle Cheng
* Added ReverseV2 to CL and Neon backends * Added Cl and Neon ReverseV2 Layer unit tests Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I646275c629caf17dac1950b0cd7083f23f87f387
2023-11-09IVGCVSW-7861 Updating tflite parser to ignore VALIDATION: subgraphs.Colm Donelan
Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: If156b975d37868db77d7c6bb75d884652278e02a
2023-11-08IVGCVSW-8140 Prelu restriction in quantization not neededTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ic3c42db6fd87b379b42d610e0d0f56f55580268d
2023-11-08Removing explicit block on non constant bias in NEON CONV2D.Colm Donelan
* Following resolution of COMPMID-6397 we will allow non const bias CONV2D to be validated by ACL. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I31c34f3c44fe96885077b3e266f840e51ecf02ec
2023-11-02IVGCVSW-7889 Add support for Signed64 data type in Cast layerTeresa Charlin
* Remove mention of "isDepthwise" variable name when not needed and therefore IgnoreUnused call * Improve error messages and change them to throws in Encoder and Decoder Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I8ce30b5075e1e47d54abc12390265ba8e9ee1405
2023-11-01Update ACL pin to 704c22f1373e1276acb43c71e7e17048271bbc03Nikhil Raj
* Update ACL pin * ACL removed softmax_layer_max_shift_exp_sum_quantized_serial cl kernel * Replace softmax_layer_max_shift_exp_sum_quantized_serial with softmax_x Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I0830605d72999d5a80f06e1b8498bc7b674195e3
2023-10-25IVGCVSW-7751 DTS: Fix Gather and GatherNd Tests in CpuRefCiara Sookarry
* Report unsupported when indices have negative values Signed-off-by: Ciara Sookarry <ciara.sookarry@arm.com> Change-Id: I9592dcd8c5556d57bedc0d2236f0338c83e597d2
2023-10-20IVGCVSW-8103 SquareDiff restriction in quantization not neededTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib49795e44ea7e4674a3b8e0df46e80c82f9a4132
2023-10-16IVGCVSW-7752 DTS: Fix QuantizePerChannel testsJohn Mcloughlin
* Added validation for scale on all Quantized types * Added Encoder for Per Axis UINT16 Symmetrical Quantized type * Added error for Per Axis Asymmetrical Quantized type not supported Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: I433519ccacd71219a92bde2b81955d6abf9219c5
2023-10-12Revert "Revert "MLCE-1093 Reshape and concat invalid results""Mike Kelly
This reverts commit 008270f8c1359a7d62c2f881326b4d3f0d8b7b56. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: If8f5151aa349ff3834f03391e813669e5c51ed66
2023-10-09Revert "IVGCVSW-7850 block non const bias on NEON Depthwise conv."Colm Donelan
This reverts commit 47016c0c74fc97cf51f90555a11238332fe9406c. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I40856ccb581bf60c8a72ecac4cfe7375cbf4b286
2023-10-05IVGCVSW-7750 DTS: Fix ElementWise isnan assertDavid Monahan
* Removed the ASSERTS in TypesUtils.cpp in favour of InvalidArgumentExceptions instead * Added a try/catch block when calling EnqueueWorkload to catch Exceptions raised by bad inputs Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Icade014ec75db13722eb5d8adc7bdb93c8862417
2023-10-03IVGCVSW-7749 DTS: Fix reshape floating point exceptionTianle Cheng
* Updated Opaque Delegate, TfliteParser, OnnxParser, and Deserializer to handle the Zero In Shape edge case Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I4a0d1e72a66de1fa56de99af9b6730a84e0ff596
2023-10-03IVGCVSW-8033 Update Arm NN to use TOSA v0.60.0Narumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: If1504534fbd7d6b317fdb93083dcdbd8b827764b
2023-09-29IVGCVSW-8055 Add support for GELU activation function.Teresa Charlin
* Add support to CpuRef, CpuAcc and GpuAcc * Add support to tflite parser, classic and opaque tflite delegates * Add support to serializer and deserializer * Add Unit tests Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ibc60ef2ef2a051e6d9af6e15d24c46316ec19de4
2023-09-28IVGCVSW-7504 Create a backend specific optimization to fuse ↵Tracy Narine
ADD+MUL+Add+(Activation) in CpuAcc * Adding CpuAcc backend optimization to fuse add+mul+add into one layer * Tests added/enhanced * Also added optional extended parameter to Graph::Print() and throw macros that could be used in place of assert Signed-off-by: Tracy Narine <tracy.narine@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I5f8d094b969a130d8c2c7b4da07426313a9fea76
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