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2021-02-15IVGCVSW-4873 Implement Pimpl Idiom for INetwork and IOptimizedNetworkFrancis Murtagh
!android-nn-driver:5042 Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Ia1ce8b839e81b46428ba0f78463e085e5906958d Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Finn Williams <Finn.Williams@arm.com>
2021-02-09MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support'Sadik Armagan
* Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators * Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators * Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8
2021-02-08IVGCVSW-4873 Implement Pimpl Idiom for IRuntimeKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I52448938735b2aa678c47e0f3061c87fa0c693b1
2021-02-03backends/reference: Add ReduceSum operation supportSadik Armagan
This patch addes ReduceSum operation support for reference backend, which computes the sum of elements across dimensions of a tensor. Changelog v1: - Fix file header descriptions. Chagelog v2: - Fix line limit issue. - Fix type conversion issue. Changelog v3: - Remove tabs. - Modify newly added file headers. Changelog v4: - Symbol on header isn't allowed so drop it from newly added file headers. Changelog v5: - Remove tabs, fix the use of brackets and align lines correctly. Changelog v6: - Add serializer and deserializer support. Changelog v7: - Fix build error add missed code. Changelog v8: - Rename ReduceSumDecriptor to ReduceDescriptor - Update m_KeepDims field data type to bool on ReduceDescriptor - Add ReduceOperation field to ReduceDescriptor - Rename ReduceSumLayer to ReduceLayer - Update ReduceLayer to use ReduceDescriptor - Update ReduceLayer::ValidateTensorShapesFromInputs() function - Rename RefReduceSumWokload to RefReduceWorkload - Update workload to use ReduceDescriptor - Update workload to use Decoders and Encoders - Remove ReduceSum.hpp and ReduceSum.cpp - Added Reduce.hpp and Reduce.cpp - Move Mean.cpp (which is implementing REDUCE_MEAN) functionality to Reduce.cpp - Update RefMeanWorkload to call Reduce function with ReduceOperation::Mean argument - Remove Mean.hpp and Mean.cpp - Update the Serializer/Deserializer ArmnnSchema.fbs for ReduceLayer, ReduceDescriptor, and ReduceOperation - Update Serializer and Deserializer for serializing/parsing ReduceLayer - Added TfLiter parser Sum test for REDUCE_SUM operator - Make corresponding changes on front-end and Ref backend to support REDUCE_SUM operator Changelog v9: - Fixed build errors. Change-Id: I8c8e034f3df73f9565b3c18eff51ecca6c542195 Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
2020-12-16IVGCVSW-5595 Fix incorrect padding value for asymmetric quantized typeNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I85f0c30757043f8c27c78d607f0f9dbbdd35b9fb
2020-11-18Fix logical vts skipNarumol Prangnawarat
* Add Boolean support for Reshape * Use LogicalUnary factory and data type for LogicalNot Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I8e072fde200b7716556ae67f79616458cf98ff20
2020-11-09IVGCVSW-5091 Add Logical ops frontend and ref implJames Conroy
* Add frontend and reference implementation for logical ops NOT, AND, OR. * Unary NOT uses existing ElementwiseUnary layer and ElementwiseUnary descriptor. * Binary AND/OR uses new layer LogicalBinary and new LogicalBinary descriptor. * Add serialization/deserializion support and add missing ElementwiseUnary deserializer code. * Add additional Boolean decoder in BaseIterator.hpp. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: Id343b01174053a166de1b98b6175e04a5065f720
2020-11-09IVGCVSW-5327 Add to Layer a binary blob to host the activation layer infoKeith Davis
Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I0a07dea96a86849701ba387dbea148909a6d729b
2020-09-24Add int32 and int64 ArgMax op supportInki Dae
This patch adds int32 and int64 ArgMax op support. Current ARMNN already has ArgMax op but not used, and it doesn't support int64 output type. So this patch adds a new type, Signed64, and also adds ArgMinMax computation function for int64 type support. In default, output tensor type of ArgMax op is int64 in case of tensorflow lite model so this patch makes a proper function - ArgMax op for int64 or int32 - to be called according to parsed output_type value. With this patch, ARMNN supports both types - int64 and int32 - for ArgMinMax op. Changelog v1: - Check if output data type of ArgMinMax op is valid or not. - Use template function to support int32 and int64 types of ArgMinMax function. - Keep using Signed32 as default data type of m_Output_Type. Change-Id: I7a8e7e38dd9e5acc81464571d8b4d51378fc7f14 Signed-off-by: Inki Dae <inki.dae@samsung.com>
2020-08-31IVGCVSW-5256 Use CreateTensorHandle() function from TensorHandleFactory in ↵Finn Williams
the tests for layers Q,R & T Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I6fc613d31785298a0b7ed18f1abdd59bafed1e8e
2020-08-31IVGCVSW-5231 Remove CreateTensorHandle in the test where there is ↵Keith Davis
NO_DEPRECATE_WARN * Done for all elementwise layers, Activation, BatchNorm, BatchToSpace Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: Id1d15a0960233026aecf7a07e0d3f006e07e4abf
2020-08-31IVGCVSW-5253 Use CreateTensorHandle() function from TensorHandleFactory in ↵Finn Williams
the tests for layers M-P Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I324eee7d750e30f714e0d346b7da7b69866ff935
2020-08-31IVGCVSW-5252 Use CreateTensorHandle() function from TensorHandleFactory in ↵Finn Williams
the tests for layers between G-L Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I197351a479fb211787bd12a73c9618d2ded95898
2020-08-31IVGCVSW-5249 Use CreateTensorHandle from ITensorHandleFactory in the test ↵Keith Davis
for all layers between C-D Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I9583adf50e67e63e73833f400d1c50fbff57f60c
2020-08-31IVGCVSW-5250 Remove CreateTensorHandle in the test for layers between E-FFinn Williams
* Refactored Floor and FullyConnected tests Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Iad87254e638bdcb5d7b334b16ec87a0c981e48a0
2020-08-28IVGCVSW-5257 'Remove CreateTensorHandle in the test for layers beginning with S'Sadik Armagan
* Re-factored SplaceToDepth, Splitter, Stack and StridedSlice unit tests to use TensorHandleFactory for creating TensorHandles Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ib22bb09cd2120c02c548099eaa06db6e6f00b15e
2020-08-27IVGCVSW-5257 'Remove CreateTensorHandle in the test for layers beginning with S'Sadik Armagan
* Re-factored SoftmaxTestImpl to use TensorHandleFactory to create TensorHandles Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I83559a89187bbed0d6f34ca589ea81c694bf5683
2020-08-27IVGCVSW-5257 'Remove CreateTensorHandle in the test for layers beginning with S'Sadik Armagan
* Re-factored SpaceToBatchNd tests to use TensorHandleFactory to create TensorHandles Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I096a6e30ecc97dd9b93b206157f16d912085703c
2020-08-27IVGCVSW-5251 'Remove CreateTensorHandle for ArgMinMaxTestImpl'Sadik Armagan
* Refactored ArgMinMax tests to use TensorHandleFactory instead of WorkloadFactory Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ibff0f9370972f9a0a977c05275cb6168f8f88ae5
2020-08-26IVGCVSW-5250 Remove CreateTensorHandle in the test for layers between E-FFinn Williams
* Added new test function to pass in the ITensorHandleFactory Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I9b2e9250200e092541e29796ec53cabd0b677acf
2020-08-25IVGCVSW-5109 'Add SupportsInPlaceComputation to TensorHandleFactories'Sadik Armagan
* Added functionality to query if TensorHandleFactory supports InPlaceComputation Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Icf5bfc5f999fc5d03681dcb8cec88d921842458b
2020-08-16IVGCVSW-5216 Remove CreateTensorHandle from TransposeTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iea9cc3a36021aac4b86ea5d8340dd8eb1f308283
2020-08-15IVGCVSW-5218 Remove CreateTensorHandle from DetectionPostProcess and PreluFrancis Murtagh
* Remove default arguments in Neon and CL causing ambiguity Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I314885719a16311b68c7bda37cd54b2ca0d14480
2020-08-12IVGCVSW-4979 Add GetTensorHandleFactory to WorkloadFactoryHelper(Ref/Ne/Cl)Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I7e4c752f396833e226d73c3569e195b796fbf482
2020-07-31IVGCVSW-4712 Fill layer datatype adjustmentsTeresa Charlin
* Input layer to be int32 instead of same type as output * Enable float16 end to end tests * Neon and Cl layer support check for backend Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6bc889077c8da63eeff66bd45730ce5d8783c419
2020-07-30IVGCVSW-5174 Fix i386 Floor and AbsTestFrancis Murtagh
* Remove QSymm16 support for Floor to match NNApi and disable RefLayerTest * Return nullptr for floor workload if quantized type * Fix SimpleAbsTest incorrect output Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I80d9e2fb78777d0a3fc7ce6d12b5eb4af3fd1d3a
2020-07-30IVGCVSW-4713 Add EndToEnd test for RANKTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ia8f237a2500986e01843defb75787694a20ba24c
2020-07-28IVGCVSW-4712 Add EndToEnd test for FILLTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ic89bcbbd580abe1b05bd26748db704e83cf65bea
2020-07-24IVGCVSW-4889/IVGCVSW-4890 CL/Neon UnitTests for align_corners & half_pixelsTeresa Charlin
*Add more UnitTests to the reference implemenation. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Idbce68baa76b049e5f741f790a5cfd75acb54a95
2020-07-23IVGCVSW-5010 Add GetCapabilities to ITensorHandleFactoryNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ie8acb9c729af4f95488aecf795f45ff12364f9ca
2020-07-07Remove new occurence of boost::polymorphic_downcastJan Eilers
Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Id9446c30f6a31c5064bab08b40805e463700072c
2020-07-06IVGCVSW-4624 Add a RANK Reference ImplementationFinn Williams
* Add Rank front end * Add Rank reference implementation * Add Rank serialization support * Add Scalar serialization support Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I06e4a468c2a84e79bae2e6c5348596bbbf853b4b
2020-06-30IVGCVSW-5007 Implement an Int32 reference Elementwise workloadFinn Williams
Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I6592169b74ac4294bc09647879aec0718c641f91
2020-06-30IVGCVSW-5036 Do not allocate memory when import is enabledNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ideaae5280702aae6c73f3b4e4cee9f71a8386fda
2020-06-24IVGCVSW-4621 Add CL FILL WorkloadSadik Armagan
* Add CL workload for Fill Operator * Enabled Fill operator tests on CL * CLFill function does not have validate() function yet IsLayerSupported() function return true at the moment * Enabled int32 to tests on backends Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I9f8cc6d1c86f832ba46a8d170572f4cfcde9ab17
2020-06-20IVGCVSW-4707 - Add AlignCorners and HalfPixelCenters to ResizeDavid Monahan
* Added AlignCorners and HalfPixelCenters Parameters to Resize * Added Unit Tests Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I83420a9bcb7beec9073d201448f64eb53090e1f1
2020-06-15IVGCVSW-4620 Add Fill Reference ImplementationRyan OShea
* Add Fill Reference Implementation * Refactor FP converter to use static_cast Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I532e2f982981d047690755fac43a0e9cf8b17dcd
2020-06-08IVGCVSW-4860 Add tests to verify QLstm projectionJames Conroy
* Adds int16 output tensor to CpuRef impl to prevent overflow when accumulating output after projection. * Adds two remaining tests to verify QLstm on CpuRef. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I93d7c64c4a9cc1012cb2bc052d598d4279fbd372
2020-06-05IVGCVSW-4904 Refactor CpuRef PAD WorkloadSadik Armagan
* Refactored templated workload creation * Added int8_t unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I018b7f9f20496b5f9d7445901fe0d3dd04199cd0
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-05-29IVGCVSW-3847 Support INT32 in Gather operatorTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ica217d3e4fbcdef1315554ea5d5c4720124696c3
2020-05-27IVGCVSW-4200 Add CL EXP WorkloadSadik Armagan
IVGCVSW-4203 Add Neon EXP Workload * Added CL EXP operator workload * Added EXP test suite * Enabled EXP tests on ACL and Ref Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I793d31af1b2e3fe86b0bec6d9e5de503c5dab970
2020-05-25IVGCVSW-4863 ADD,SUB,DIV,MUL,MAXIMUM and MINIMUM int32 VTS testTeresa Charlin
skipped in CpuRef Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I1c870ac258e8c3805a95b259cb40731f8e81541e
2020-05-25IVGCVSW-4604 ARGMINMAX float16 VTS test skipped in CpuRefTeresa Charlin
Change-Id: I75cca9804a67f629cddc83671397a84640e9bf0e Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
2020-05-25IVGCVSW-4611 PRELU float16 VTS test skipped in CpuRefTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Id908e0bcbefd3284da51cdbe8ec0c2181b9b553e
2020-05-22Fix some build errors spotted on Windows:Rob Hughes
* Use exact floating point constants for min/max values * Rename test case so it doesn't collide with a function name Change-Id: Icf03cfd8fedd505d02cd7f0a150502557939b903 Signed-off-by: Robert Hughes <robert.hughes@arm.com>
2020-05-21IVGCVSW-4452 Add QLstm EndToEndTestJames Conroy
* QLstm EndToEndTest added for Ref, NEON and CL. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: Icd2c878541f6304d726202a93d71ff3d79f6f054
2020-05-15IVGCVSW-4831 Fix Packet header includes in backendsFinn Williams
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Iedfcf0ef487bd7836b1bc4ba8a0e4337dc4da391
2020-05-02IVGCVSW-4449 Add QLstm ref implementationJames Conroy
* Adds ref implemenation for new HAL 1.3 operator, QLstm. * Adds Layer and CreateWorkload unit tests. * Adds WorkloadData validate for QLstm. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I8a721f07ff06105e6495a1a0561b9503aa8146dc
2020-04-30IVGCVSW-4753 Fix CpuAcc Hal 1.3 Softmax FailuresSadik Armagan
* Refactor Neon Softmax workload to accept supported data types Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I54aa72d5cbb862cafcc1eabe48f6a00d61050cd7
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