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-rw-r--r--src/backends/reference/workloads/CMakeLists.txt6
-rw-r--r--src/backends/reference/workloads/Mean.hpp22
-rw-r--r--src/backends/reference/workloads/Reduce.cpp (renamed from src/backends/reference/workloads/Mean.cpp)48
-rw-r--r--src/backends/reference/workloads/Reduce.hpp24
-rw-r--r--src/backends/reference/workloads/RefMeanWorkload.cpp9
-rw-r--r--src/backends/reference/workloads/RefReduceWorkload.cpp42
-rw-r--r--src/backends/reference/workloads/RefReduceWorkload.hpp23
-rw-r--r--src/backends/reference/workloads/RefWorkloads.hpp1
8 files changed, 129 insertions, 46 deletions
diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt
index 1b20e5bf2d..1f4298be5d 100644
--- a/src/backends/reference/workloads/CMakeLists.txt
+++ b/src/backends/reference/workloads/CMakeLists.txt
@@ -44,8 +44,6 @@ list(APPEND armnnRefBackendWorkloads_sources
LstmUtils.hpp
LstmUtils.cpp
Maximum.hpp
- Mean.cpp
- Mean.hpp
Concatenate.hpp
Concatenate.cpp
Minimum.hpp
@@ -55,6 +53,8 @@ list(APPEND armnnRefBackendWorkloads_sources
Pooling2d.hpp
PreluImpl.cpp
PreluImpl.hpp
+ Reduce.cpp
+ Reduce.hpp
RefActivationWorkload.cpp
RefActivationWorkload.hpp
RefArgMinMaxWorkload.cpp
@@ -132,6 +132,8 @@ list(APPEND armnnRefBackendWorkloads_sources
RefQLstmWorkload.cpp
RefQLstmWorkload.hpp
RefRankWorkload.hpp
+ RefReduceWorkload.cpp
+ RefReduceWorkload.hpp
RefReshapeWorkload.cpp
RefReshapeWorkload.hpp
RefResizeBilinearWorkload.cpp
diff --git a/src/backends/reference/workloads/Mean.hpp b/src/backends/reference/workloads/Mean.hpp
deleted file mode 100644
index dfb0302bf9..0000000000
--- a/src/backends/reference/workloads/Mean.hpp
+++ /dev/null
@@ -1,22 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#pragma once
-
-#include "armnn/DescriptorsFwd.hpp"
-#include "armnn/Tensor.hpp"
-#include "BaseIterator.hpp"
-
-#include <vector>
-
-namespace armnn
-{
-void Mean(const TensorInfo& inputInfo,
- const TensorInfo& outputInfo,
- const std::vector<unsigned int>& axis,
- Decoder<float>& input,
- Encoder<float>& output);
-} //namespace armnn
-
diff --git a/src/backends/reference/workloads/Mean.cpp b/src/backends/reference/workloads/Reduce.cpp
index fe34efe0c7..5375c7163a 100644
--- a/src/backends/reference/workloads/Mean.cpp
+++ b/src/backends/reference/workloads/Reduce.cpp
@@ -1,13 +1,14 @@
//
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
// SPDX-License-Identifier: MIT
//
-#include "Mean.hpp"
-#include <backendsCommon/WorkloadData.hpp>
+#include "Reduce.hpp"
#include <armnn/utility/NumericCast.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+
#include <cmath>
#include <cstddef>
#include <functional>
@@ -15,6 +16,7 @@
namespace armnn
{
+
bool NextIndex(const unsigned int numDims, const armnn::TensorShape& dims, std::vector<unsigned int>& current)
{
unsigned int carry = 1;
@@ -64,18 +66,16 @@ unsigned int ReducedOutputOffset(const unsigned int numDims,
}
return offset;
}
-} // namespace
-namespace armnn
-{
-void Mean(const armnn::TensorInfo& inputInfo,
- const armnn::TensorInfo& outputInfo,
- const std::vector<unsigned int>& axis,
- Decoder<float>& input,
- Encoder<float>& output)
-{
- unsigned int inputNumDims = inputInfo.GetNumDimensions();
+void Reduce(const TensorInfo& inputInfo,
+ const TensorInfo& outputInfo,
+ Decoder<float>& input,
+ Encoder<float>& output,
+ const std::vector<uint32_t> axis,
+ const ReduceOperation reduceOperation)
+{
+ unsigned int inputNumDims = inputInfo.GetNumDimensions();
unsigned int outputNumDims = outputInfo.GetNumDimensions();
armnn::TensorShape outputDims = outputInfo.GetShape();
@@ -106,10 +106,10 @@ void Mean(const armnn::TensorInfo& inputInfo,
std::vector<unsigned int> resolvedAxis = axis;
if (resolvedAxis.empty())
{
- for (unsigned int idx = 0; idx < inputNumDims; ++idx)
- {
- resolvedAxis.push_back(idx);
- }
+ for (unsigned int idx = 0; idx < inputNumDims; ++idx)
+ {
+ resolvedAxis.push_back(idx);
+ }
}
auto numResolvedAxis = armnn::numeric_cast<unsigned int>(resolvedAxis.size());
@@ -129,15 +129,23 @@ void Mean(const armnn::TensorInfo& inputInfo,
{
unsigned int current = inputDims[resolvedAxis[idx]];
ARMNN_ASSERT(armnn::numeric_cast<float>(current) <
- (std::numeric_limits<float>::max() / armnn::numeric_cast<float>(numElementsInAxis)));
+ (std::numeric_limits<float>::max() / armnn::numeric_cast<float>(numElementsInAxis)));
numElementsInAxis *= current;
}
if (numElementsInAxis > 0) {
for (unsigned int idx = 0; idx < numOutputs; ++idx)
{
output[idx];
- output.Set(tempSum[idx] / armnn::numeric_cast<float>(numElementsInAxis));
+ if (reduceOperation == ReduceOperation::Sum)
+ {
+ output.Set(tempSum[idx]);
+ }
+ else if (reduceOperation == ReduceOperation::Mean)
+ {
+ output.Set(tempSum[idx] / armnn::numeric_cast<float>(numElementsInAxis));
+ }
}
}
}
-} //namespace armnn
+
+} //namespace armnn \ No newline at end of file
diff --git a/src/backends/reference/workloads/Reduce.hpp b/src/backends/reference/workloads/Reduce.hpp
new file mode 100644
index 0000000000..ad777adcf5
--- /dev/null
+++ b/src/backends/reference/workloads/Reduce.hpp
@@ -0,0 +1,24 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include "BaseIterator.hpp"
+#include "Decoders.hpp"
+#include "Encoders.hpp"
+
+#include <armnn/Tensor.hpp>
+
+namespace armnn
+{
+
+void Reduce(const TensorInfo& inputInfo,
+ const TensorInfo& outputInfo,
+ Decoder<float>& input,
+ Encoder<float>& output,
+ const std::vector<uint32_t> axis,
+ const ReduceOperation reduceOperation);
+
+} //namespace armnn
diff --git a/src/backends/reference/workloads/RefMeanWorkload.cpp b/src/backends/reference/workloads/RefMeanWorkload.cpp
index 375ab395be..00e59bca4c 100644
--- a/src/backends/reference/workloads/RefMeanWorkload.cpp
+++ b/src/backends/reference/workloads/RefMeanWorkload.cpp
@@ -5,7 +5,7 @@
#include "RefMeanWorkload.hpp"
-#include "Mean.hpp"
+#include "Reduce.hpp"
#include "RefWorkloadUtils.hpp"
#include "Profiling.hpp"
@@ -28,7 +28,12 @@ void RefMeanWorkload::Execute() const
auto inputDecoder = MakeDecoder<float>(inputInfo, m_Data.m_Inputs[0]->Map());
auto outputEncoder = MakeEncoder<float>(outputInfo, m_Data.m_Outputs[0]->Map());
- Mean(inputInfo, outputInfo, m_Data.m_Parameters.m_Axis, *inputDecoder, *outputEncoder);
+ Reduce(inputInfo,
+ outputInfo,
+ *inputDecoder,
+ *outputEncoder,
+ m_Data.m_Parameters.m_Axis,
+ armnn::ReduceOperation::Mean);
}
} //namespace armnn
diff --git a/src/backends/reference/workloads/RefReduceWorkload.cpp b/src/backends/reference/workloads/RefReduceWorkload.cpp
new file mode 100644
index 0000000000..7a46ff9ffc
--- /dev/null
+++ b/src/backends/reference/workloads/RefReduceWorkload.cpp
@@ -0,0 +1,42 @@
+//
+// Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "RefReduceWorkload.hpp"
+
+#include "Reduce.hpp"
+#include "RefWorkloadUtils.hpp"
+#include "BaseIterator.hpp"
+#include "Profiling.hpp"
+
+namespace armnn
+{
+
+RefReduceWorkload::RefReduceWorkload(
+ const ReduceQueueDescriptor& descriptor,
+ const WorkloadInfo& info)
+ : BaseWorkload<ReduceQueueDescriptor>(descriptor, info) {}
+
+void RefReduceWorkload::Execute() const
+{
+ ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefReduceWorkload_Execute");
+
+ const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]);
+ const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]);
+
+ std::unique_ptr<Decoder<float>> decoderPtr = MakeDecoder<float>(inputInfo, m_Data.m_Inputs[0]->Map());
+ Decoder<float>& decoder = *decoderPtr;
+
+ std::unique_ptr<Encoder<float>> encoderPtr = MakeEncoder<float>(outputInfo, m_Data.m_Outputs[0]->Map());
+ Encoder<float>& encoder = *encoderPtr;
+
+ Reduce(inputInfo,
+ outputInfo,
+ decoder,
+ encoder,
+ m_Data.m_Parameters.m_vAxis,
+ m_Data.m_Parameters.m_ReduceOperation);
+}
+
+} //namespace armnn
diff --git a/src/backends/reference/workloads/RefReduceWorkload.hpp b/src/backends/reference/workloads/RefReduceWorkload.hpp
new file mode 100644
index 0000000000..1d551acb4a
--- /dev/null
+++ b/src/backends/reference/workloads/RefReduceWorkload.hpp
@@ -0,0 +1,23 @@
+//
+// Copyright © 2020 Samsung Electronics Co Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+
+namespace armnn
+{
+
+class RefReduceWorkload : public BaseWorkload<ReduceQueueDescriptor>
+{
+public:
+ explicit RefReduceWorkload(const ReduceQueueDescriptor& descriptor,
+ const WorkloadInfo& info);
+
+ virtual void Execute() const override;
+};
+
+} //namespace armnn
diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp
index 390b2a8d55..989644f633 100644
--- a/src/backends/reference/workloads/RefWorkloads.hpp
+++ b/src/backends/reference/workloads/RefWorkloads.hpp
@@ -54,6 +54,7 @@
#include "RefQLstmWorkload.hpp"
#include "RefQuantizeWorkload.hpp"
#include "RefRankWorkload.hpp"
+#include "RefReduceWorkload.hpp"
#include "RefReshapeWorkload.hpp"
#include "RefResizeBilinearWorkload.hpp"
#include "RefResizeWorkload.hpp"
generated by cgit v1.2.1 (git 2.23.0) at 2024-06-09 14:12:39 +0000