MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support'

* Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators
* Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators
* Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators

Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8

4 files changed, 99 insertions, 0 deletions

diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt
index 7427ea018d..3a1b6b8432 100644
--- a/src/backends/cl/workloads/CMakeLists.txt
+++ b/src/backends/cl/workloads/CMakeLists.txt
@@ -87,6 +87,8 @@ list(APPEND armnnClBackendWorkloads_sources
     ClQuantizeWorkload.cpp
     ClQuantizeWorkload.hpp
     ClRankWorkload.hpp
+    ClReduceWorkload.cpp
+    ClReduceWorkload.hpp
     ClReshapeWorkload.cpp
     ClReshapeWorkload.hpp
     ClResizeWorkload.cpp
diff --git a/src/backends/cl/workloads/ClReduceWorkload.cpp b/src/backends/cl/workloads/ClReduceWorkload.cpp
new file mode 100644
index 0000000000..6f594ff7a9
--- /dev/null
+++ b/src/backends/cl/workloads/ClReduceWorkload.cpp
@@ -0,0 +1,66 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "ClReduceWorkload.hpp"
+
+#include <cl/ClTensorHandle.hpp>
+#include <aclCommon/ArmComputeUtils.hpp>
+#include <aclCommon/ArmComputeTensorUtils.hpp>
+
+#include "ClWorkloadUtils.hpp"
+
+namespace armnn
+{
+using namespace armcomputetensorutils;
+
+arm_compute::Status ClReduceWorkloadValidate(const TensorInfo& input,
+                                             const TensorInfo& output,
+                                             const ReduceDescriptor& desc)
+{
+    const arm_compute::TensorInfo aclInputInfo  = armcomputetensorutils::BuildArmComputeTensorInfo(input);
+    const arm_compute::TensorInfo aclOutputInfo = armcomputetensorutils::BuildArmComputeTensorInfo(output);
+    if (!desc.m_vAxis.empty() && desc.m_vAxis.size() > 1)
+    {
+        return arm_compute::Status(arm_compute::ErrorCode::RUNTIME_ERROR,
+                                   "ClReduceWorkload: Reduction is supported only on 1 axis.");
+    }
+
+    arm_compute::Coordinates coords = BuildArmComputeReductionCoordinates(aclInputInfo.num_dimensions(),
+                                                                          input.GetNumDimensions(),
+                                                                          desc.m_vAxis);
+
+
+    return arm_compute::CLReductionOperation::validate(&aclInputInfo,
+                                                       &aclOutputInfo,
+                                                       static_cast<unsigned int>(coords[0]),
+                                                       ConvertReductionOperationToAcl(desc),
+                                                       desc.m_KeepDims);
+}
+
+ClReduceWorkload::ClReduceWorkload(const ReduceQueueDescriptor& descriptor, const WorkloadInfo& info)
+    : BaseWorkload<ReduceQueueDescriptor>(descriptor, info)
+{
+    m_Data.ValidateInputsOutputs("ClReduceWorkload", 1, 1);
+
+    arm_compute::ICLTensor& input  = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
+    arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
+
+    arm_compute::Coordinates coords = BuildArmComputeReductionCoordinates(input.info()->num_dimensions(),
+                                                                          info.m_InputTensorInfos[0].GetNumDimensions(),
+                                                                          m_Data.m_Parameters.m_vAxis);
+    m_Layer.configure(&input,
+                      &output,
+                      static_cast<unsigned int>(coords[0]),
+                      ConvertReductionOperationToAcl(m_Data.m_Parameters),
+                      m_Data.m_Parameters.m_KeepDims);
+}
+
+void ClReduceWorkload::Execute() const
+{
+    ARMNN_SCOPED_PROFILING_EVENT_CL("ClReduceWorkload_Execute");
+    m_Layer.run();
+}
+
+} //namespace armnn
diff --git a/src/backends/cl/workloads/ClReduceWorkload.hpp b/src/backends/cl/workloads/ClReduceWorkload.hpp
new file mode 100644
index 0000000000..8481eeea5a
--- /dev/null
+++ b/src/backends/cl/workloads/ClReduceWorkload.hpp
@@ -0,0 +1,30 @@
+//
+// Copyright © 2021 Arm Ltd and Contributors. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+
+#include <arm_compute/runtime/CL/functions/CLReductionOperation.h>
+
+namespace armnn
+{
+
+arm_compute::Status ClReduceWorkloadValidate(const TensorInfo& input,
+                                             const TensorInfo& output,
+                                             const ReduceDescriptor& desc);
+
+class ClReduceWorkload : public BaseWorkload<ReduceQueueDescriptor>
+{
+public:
+    ClReduceWorkload(const ReduceQueueDescriptor& descriptor, const WorkloadInfo& info);
+
+    void Execute() const override;
+
+private:
+    mutable arm_compute::CLReductionOperation m_Layer;
+};
+
+} //namespace armnn
diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp
index 0045e7a77f..f99a9fa11b 100644
--- a/src/backends/cl/workloads/ClWorkloads.hpp
+++ b/src/backends/cl/workloads/ClWorkloads.hpp
@@ -44,6 +44,7 @@
 #include "ClQuantizeWorkload.hpp"
 #include "ClQuantizedLstmWorkload.hpp"
 #include "ClRankWorkload.hpp"
+#include "ClReduceWorkload.hpp"
 #include "ClReshapeWorkload.hpp"
 #include "ClResizeWorkload.hpp"
 #include "ClRsqrtWorkload.hpp"