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| author | Nattapat Chaimanowong <nattapat.chaimanowong@arm.com> | 2018-10-17 15:19:14 +0100 |
|---|---|---|
| committer | Matthew Bentham <matthew.bentham@arm.com> | 2018-10-22 16:57:54 +0100 |
| commit | b66504b654a85c81557c5d003fb5f0d6808f1482 (patch) | |
| tree | c81597f36e560f87a8401a72a3617c45aa1bdb3b /src/armnnTfLiteParser/TfLiteParser.hpp | |
| parent | 3dc4303c94cf3f5976e495233f663ff56089e53a (diff) | |
| download | armnn-b66504b654a85c81557c5d003fb5f0d6808f1482.tar.gz | |
IVGCVSW-2030 and IVGCVSW-2031 Add MaxPooling support and unit test to TfLite Parser
Change-Id: I3aea8ea6d018900682d278f28a50e40cf2f963fe
Diffstat (limited to 'src/armnnTfLiteParser/TfLiteParser.hpp')
| -rw-r--r-- | src/armnnTfLiteParser/TfLiteParser.hpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/armnnTfLiteParser/TfLiteParser.hpp b/src/armnnTfLiteParser/TfLiteParser.hpp index 620648a0c3..35f0b64419 100644 --- a/src/armnnTfLiteParser/TfLiteParser.hpp +++ b/src/armnnTfLiteParser/TfLiteParser.hpp @@ -6,6 +6,7 @@ #include "armnn/INetwork.hpp" #include "armnnTfLiteParser/ITfLiteParser.hpp" +#include "armnn/Types.hpp" #include <schema_generated.h> #include <functional> @@ -93,12 +94,15 @@ private: void ParseConcatenation(size_t subgraphIndex, size_t operatorIndex); void ParseConv2D(size_t subgraphIndex, size_t operatorIndex); void ParseDepthwiseConv2D(size_t subgraphIndex, size_t operatorIndex); + void ParseMaxPool2D(size_t subgraphIndex, size_t operatorIndex); void ParseRelu(size_t subgraphIndex, size_t operatorIndex); void ParseRelu6(size_t subgraphIndex, size_t operatorIndex); void ParseReshape(size_t subgraphIndex, size_t operatorIndex); void ParseSoftmax(size_t subgraphIndex, size_t operatorIndex); void ParseSqueeze(size_t subgraphIndex, size_t operatorIndex); + void ParsePool(size_t subgraphIndex, size_t operatorIndex, armnn::PoolingAlgorithm algorithm); + void RegisterProducerOfTensor(size_t subgraphIndex, size_t tensorIndex, armnn::IOutputSlot* slot); void RegisterConsumerOfTensor(size_t subgraphIndex, size_t tensorIndex, armnn::IInputSlot* slot); void RegisterInputSlots(size_t subgraphIndex, |