IVGCVSW-1843 : refactor ClAdditionWorkload and ClSubtractionWorkload

Change-Id: I0ca9f16217f8e32bb57a49b841611f10dabf021a

12 files changed, 18 insertions, 178 deletions

diff --git a/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp b/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp
deleted file mode 100644
index b51d8a7efd..0000000000
--- a/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.cpp
+++ /dev/null
@@ -1,22 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#include "ClAdditionFloatWorkload.hpp"
-
-#include "backends/ClTensorHandle.hpp"
-#include "backends/CpuTensorHandle.hpp"
-#include "backends/ArmComputeTensorUtils.hpp"
-
-namespace armnn
-{
-using namespace armcomputetensorutils;
-
-void ClAdditionFloatWorkload::Execute() const
-{
-    ARMNN_SCOPED_PROFILING_EVENT_CL("ClAdditionFloatWorkload_Execute");
-    ClAdditionBaseWorkload::Execute();
-}
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.hpp b/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.hpp
deleted file mode 100644
index de33ca6ce4..0000000000
--- a/src/armnn/backends/ClWorkloads/ClAdditionFloatWorkload.hpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#pragma once
-
-#include "ClAdditionBaseWorkload.hpp"
-
-namespace armnn
-{
-
-class ClAdditionFloatWorkload : public ClAdditionBaseWorkload<DataType::Float16, DataType::Float32>
-{
-public:
-    using ClAdditionBaseWorkload<DataType::Float16, DataType::Float32>::ClAdditionBaseWorkload;
-    void Execute() const override;
-};
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClAdditionUint8Workload.cpp b/src/armnn/backends/ClWorkloads/ClAdditionUint8Workload.cpp
deleted file mode 100644
index 57b9062c15..0000000000
--- a/src/armnn/backends/ClWorkloads/ClAdditionUint8Workload.cpp
+++ /dev/null
@@ -1,18 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#include "ClAdditionUint8Workload.hpp"
-
-namespace armnn
-{
-using namespace armcomputetensorutils;
-
-void ClAdditionUint8Workload::Execute() const
-{
-    ARMNN_SCOPED_PROFILING_EVENT_CL("ClAdditionUint8Workload_Execute");
-    ClAdditionBaseWorkload::Execute();
-}
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClAdditionUint8Workload.hpp b/src/armnn/backends/ClWorkloads/ClAdditionUint8Workload.hpp
deleted file mode 100644
index d127e7e5c3..0000000000
--- a/src/armnn/backends/ClWorkloads/ClAdditionUint8Workload.hpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#pragma once
-
-#include "ClAdditionBaseWorkload.hpp"
-
-namespace armnn
-{
-
-class ClAdditionUint8Workload : public ClAdditionBaseWorkload<DataType::QuantisedAsymm8>
-{
-public:
-    using ClAdditionBaseWorkload<DataType::QuantisedAsymm8>::ClAdditionBaseWorkload;
-    void Execute() const override;
-};
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClAdditionBaseWorkload.cpp b/src/armnn/backends/ClWorkloads/ClAdditionWorkload.cpp
index eb14aa3891..0bba327bef 100644
--- a/src/armnn/backends/ClWorkloads/ClAdditionBaseWorkload.cpp
+++ b/src/armnn/backends/ClWorkloads/ClAdditionWorkload.cpp
@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: MIT
 //
 
-#include "ClAdditionBaseWorkload.hpp"
+#include "ClAdditionWorkload.hpp"
 
 #include "backends/ClTensorHandle.hpp"
 #include "backends/CpuTensorHandle.hpp"
@@ -16,11 +16,11 @@ using namespace armcomputetensorutils;
 static constexpr arm_compute::ConvertPolicy g_AclConvertPolicy = arm_compute::ConvertPolicy::SATURATE;
 
 template <armnn::DataType... T>
-ClAdditionBaseWorkload<T...>::ClAdditionBaseWorkload(const AdditionQueueDescriptor& descriptor,
+ClAdditionWorkload<T...>::ClAdditionWorkload(const AdditionQueueDescriptor& descriptor,
                                                   const WorkloadInfo& info)
     : TypedWorkload<AdditionQueueDescriptor, T...>(descriptor, info)
 {
-    this->m_Data.ValidateInputsOutputs("ClAdditionBaseWorkload", 2, 1);
+    this->m_Data.ValidateInputsOutputs("ClAdditionWorkload", 2, 1);
 
     arm_compute::ICLTensor& input0 = static_cast<IClTensorHandle*>(this->m_Data.m_Inputs[0])->GetTensor();
     arm_compute::ICLTensor& input1 = static_cast<IClTensorHandle*>(this->m_Data.m_Inputs[1])->GetTensor();
@@ -29,9 +29,9 @@ ClAdditionBaseWorkload<T...>::ClAdditionBaseWorkload(const AdditionQueueDescript
 }
 
 template <armnn::DataType... T>
-void ClAdditionBaseWorkload<T...>::Execute() const
+void ClAdditionWorkload<T...>::Execute() const
 {
-    ARMNN_SCOPED_PROFILING_EVENT_CL("ClAdditionBaseWorkload_Execute");
+    ARMNN_SCOPED_PROFILING_EVENT_CL("ClAdditionWorkload_Execute");
     m_Layer.run();
 }
 
@@ -60,5 +60,5 @@ bool ClAdditionValidate(const TensorInfo& input0,
 
 } //namespace armnn
 
-template class armnn::ClAdditionBaseWorkload<armnn::DataType::Float16, armnn::DataType::Float32>;
-template class armnn::ClAdditionBaseWorkload<armnn::DataType::QuantisedAsymm8>;
+template class armnn::ClAdditionWorkload<armnn::DataType::Float16, armnn::DataType::Float32>;
+template class armnn::ClAdditionWorkload<armnn::DataType::QuantisedAsymm8>;
diff --git a/src/armnn/backends/ClWorkloads/ClAdditionBaseWorkload.hpp b/src/armnn/backends/ClWorkloads/ClAdditionWorkload.hpp
index b3bf1fe597..8af8f23788 100644
--- a/src/armnn/backends/ClWorkloads/ClAdditionBaseWorkload.hpp
+++ b/src/armnn/backends/ClWorkloads/ClAdditionWorkload.hpp
@@ -11,10 +11,10 @@ namespace armnn
 {
 
 template <armnn::DataType... dataTypes>
-class ClAdditionBaseWorkload : public TypedWorkload<AdditionQueueDescriptor, dataTypes...>
+class ClAdditionWorkload : public TypedWorkload<AdditionQueueDescriptor, dataTypes...>
 {
 public:
-    ClAdditionBaseWorkload(const AdditionQueueDescriptor& descriptor, const WorkloadInfo& info);
+    ClAdditionWorkload(const AdditionQueueDescriptor& descriptor, const WorkloadInfo& info);
 
     void Execute() const override;
 
diff --git a/src/armnn/backends/ClWorkloads/ClSubtractionFloatWorkload.cpp b/src/armnn/backends/ClWorkloads/ClSubtractionFloatWorkload.cpp
deleted file mode 100644
index 3321e20100..0000000000
--- a/src/armnn/backends/ClWorkloads/ClSubtractionFloatWorkload.cpp
+++ /dev/null
@@ -1,22 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#include "ClSubtractionFloatWorkload.hpp"
-
-#include "backends/ClTensorHandle.hpp"
-#include "backends/CpuTensorHandle.hpp"
-#include "backends/ArmComputeTensorUtils.hpp"
-
-namespace armnn
-{
-using namespace armcomputetensorutils;
-
-void ClSubtractionFloatWorkload::Execute() const
-{
-    ARMNN_SCOPED_PROFILING_EVENT_CL("ClSubtractionFloatWorkload_Execute");
-    ClSubtractionBaseWorkload::Execute();
-}
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClSubtractionFloatWorkload.hpp b/src/armnn/backends/ClWorkloads/ClSubtractionFloatWorkload.hpp
deleted file mode 100644
index 34a5e40983..0000000000
--- a/src/armnn/backends/ClWorkloads/ClSubtractionFloatWorkload.hpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#pragma once
-
-#include "ClSubtractionBaseWorkload.hpp"
-
-namespace armnn
-{
-
-class ClSubtractionFloatWorkload : public ClSubtractionBaseWorkload<DataType::Float16, DataType::Float32>
-{
-public:
-    using ClSubtractionBaseWorkload<DataType::Float16, DataType::Float32>::ClSubtractionBaseWorkload;
-    void Execute() const override;
-};
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClSubtractionUint8Workload.cpp b/src/armnn/backends/ClWorkloads/ClSubtractionUint8Workload.cpp
deleted file mode 100644
index 966068d648..0000000000
--- a/src/armnn/backends/ClWorkloads/ClSubtractionUint8Workload.cpp
+++ /dev/null
@@ -1,18 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#include "ClSubtractionUint8Workload.hpp"
-
-namespace armnn
-{
-using namespace armcomputetensorutils;
-
-void ClSubtractionUint8Workload::Execute() const
-{
-    ARMNN_SCOPED_PROFILING_EVENT_CL("ClSubtractionUint8Workload_Execute");
-    ClSubtractionBaseWorkload::Execute();
-}
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClSubtractionUint8Workload.hpp b/src/armnn/backends/ClWorkloads/ClSubtractionUint8Workload.hpp
deleted file mode 100644
index 15b2059615..0000000000
--- a/src/armnn/backends/ClWorkloads/ClSubtractionUint8Workload.hpp
+++ /dev/null
@@ -1,20 +0,0 @@
-//
-// Copyright © 2017 Arm Ltd. All rights reserved.
-// SPDX-License-Identifier: MIT
-//
-
-#pragma once
-
-#include "ClSubtractionBaseWorkload.hpp"
-
-namespace armnn
-{
-
-class ClSubtractionUint8Workload : public ClSubtractionBaseWorkload<DataType::QuantisedAsymm8>
-{
-public:
-    using ClSubtractionBaseWorkload<DataType::QuantisedAsymm8>::ClSubtractionBaseWorkload;
-    void Execute() const override;
-};
-
-} //namespace armnn
diff --git a/src/armnn/backends/ClWorkloads/ClSubtractionBaseWorkload.cpp b/src/armnn/backends/ClWorkloads/ClSubtractionWorkload.cpp
index 2145ed4a2a..ec8bfc6351 100644
--- a/src/armnn/backends/ClWorkloads/ClSubtractionBaseWorkload.cpp
+++ b/src/armnn/backends/ClWorkloads/ClSubtractionWorkload.cpp
@@ -3,7 +3,7 @@
 // SPDX-License-Identifier: MIT
 //
 
-#include "ClSubtractionBaseWorkload.hpp"
+#include "ClSubtractionWorkload.hpp"
 
 #include "backends/ClTensorHandle.hpp"
 #include "backends/CpuTensorHandle.hpp"
@@ -16,11 +16,11 @@ using namespace armcomputetensorutils;
 static constexpr arm_compute::ConvertPolicy g_AclConvertPolicy = arm_compute::ConvertPolicy::SATURATE;
 
 template <armnn::DataType... T>
-ClSubtractionBaseWorkload<T...>::ClSubtractionBaseWorkload(const SubtractionQueueDescriptor& descriptor,
+ClSubtractionWorkload<T...>::ClSubtractionWorkload(const SubtractionQueueDescriptor& descriptor,
                                                            const WorkloadInfo& info)
     : TypedWorkload<SubtractionQueueDescriptor, T...>(descriptor, info)
 {
-    this->m_Data.ValidateInputsOutputs("ClSubtractionBaseWorkload", 2, 1);
+    this->m_Data.ValidateInputsOutputs("ClSubtractionWorkload", 2, 1);
 
     arm_compute::ICLTensor& input0 = static_cast<IClTensorHandle*>(this->m_Data.m_Inputs[0])->GetTensor();
     arm_compute::ICLTensor& input1 = static_cast<IClTensorHandle*>(this->m_Data.m_Inputs[1])->GetTensor();
@@ -29,9 +29,9 @@ ClSubtractionBaseWorkload<T...>::ClSubtractionBaseWorkload(const SubtractionQueu
 }
 
 template <armnn::DataType... T>
-void ClSubtractionBaseWorkload<T...>::Execute() const
+void ClSubtractionWorkload<T...>::Execute() const
 {
-    ARMNN_SCOPED_PROFILING_EVENT_CL("ClSubtractionBaseWorkload_Execute");
+    ARMNN_SCOPED_PROFILING_EVENT_CL("ClSubtractionWorkload_Execute");
     m_Layer.run();
 }
 
@@ -60,5 +60,5 @@ bool ClSubtractionValidate(const TensorInfo& input0,
 
 } //namespace armnn
 
-template class armnn::ClSubtractionBaseWorkload<armnn::DataType::Float16, armnn::DataType::Float32>;
-template class armnn::ClSubtractionBaseWorkload<armnn::DataType::QuantisedAsymm8>;
+template class armnn::ClSubtractionWorkload<armnn::DataType::Float16, armnn::DataType::Float32>;
+template class armnn::ClSubtractionWorkload<armnn::DataType::QuantisedAsymm8>;
diff --git a/src/armnn/backends/ClWorkloads/ClSubtractionBaseWorkload.hpp b/src/armnn/backends/ClWorkloads/ClSubtractionWorkload.hpp
index e4595d405a..422e6a7379 100644
--- a/src/armnn/backends/ClWorkloads/ClSubtractionBaseWorkload.hpp
+++ b/src/armnn/backends/ClWorkloads/ClSubtractionWorkload.hpp
@@ -11,10 +11,10 @@ namespace armnn
 {
 
 template <armnn::DataType... dataTypes>
-class ClSubtractionBaseWorkload : public TypedWorkload<SubtractionQueueDescriptor, dataTypes...>
+class ClSubtractionWorkload : public TypedWorkload<SubtractionQueueDescriptor, dataTypes...>
 {
 public:
-    ClSubtractionBaseWorkload(const SubtractionQueueDescriptor& descriptor, const WorkloadInfo& info);
+    ClSubtractionWorkload(const SubtractionQueueDescriptor& descriptor, const WorkloadInfo& info);
 
     void Execute() const override;