Update Doxygen for 23.11

Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I47cd933f5002cb94a73aa97689d7b3d9c93cb849

1 files changed, 4 insertions, 4 deletions

diff --git a/latest/_neon_unidirectional_sequence_lstm_workload_8hpp_source.html b/latest/_neon_unidirectional_sequence_lstm_workload_8hpp_source.html
index 410bf92d18..69e033669c 100644
--- a/latest/_neon_unidirectional_sequence_lstm_workload_8hpp_source.html
+++ b/latest/_neon_unidirectional_sequence_lstm_workload_8hpp_source.html
@@ -36,7 +36,7 @@
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-   &#160;<span id="projectnumber">23.08</span>
+   &#160;<span id="projectnumber">23.11</span>
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@@ -199,18 +199,18 @@ $(document).ready(function(){initNavTree('_neon_unidirectional_sequence_lstm_wor
 <div class="ttc" id="a_workload_8hpp_html"><div class="ttname"><a href="_workload_8hpp.html">Workload.hpp</a></div></div>
 <div class="ttc" id="anamespacearmnn_html_a4dc0adc6737b5944e7671bee71788407acaf9b6b99962bf5c2264824231d7a40c"><div class="ttname"><a href="namespacearmnn.html#a4dc0adc6737b5944e7671bee71788407acaf9b6b99962bf5c2264824231d7a40c">armnn::BoostLogSeverityMapping::info</a></div><div class="ttdeci">@ info</div></div>
 <div class="ttc" id="aclassarmnn_1_1_neon_unidirectional_sequence_lstm_workload_html_a39a30590f33a409c3c39181d446621aa"><div class="ttname"><a href="classarmnn_1_1_neon_unidirectional_sequence_lstm_workload.html#a39a30590f33a409c3c39181d446621aa">armnn::NeonUnidirectionalSequenceLstmWorkload::NeonUnidirectionalSequenceLstmWorkload</a></div><div class="ttdeci">NeonUnidirectionalSequenceLstmWorkload(const UnidirectionalSequenceLstmQueueDescriptor &amp;descriptor, const WorkloadInfo &amp;info)</div><div class="ttdef"><b>Definition:</b> <a href="_neon_unidirectional_sequence_lstm_workload_8cpp_source.html#l00033">NeonUnidirectionalSequenceLstmWorkload.cpp:33</a></div></div>
-<div class="ttc" id="astructarmnn_1_1_lstm_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_lstm_descriptor.html">armnn::LstmDescriptor</a></div><div class="ttdoc">An LstmDescriptor for the LstmLayer.</div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l01081">Descriptors.hpp:1081</a></div></div>
+<div class="ttc" id="astructarmnn_1_1_lstm_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_lstm_descriptor.html">armnn::LstmDescriptor</a></div><div class="ttdoc">An LstmDescriptor for the LstmLayer.</div><div class="ttdef"><b>Definition:</b> <a href="_descriptors_8hpp_source.html#l01102">Descriptors.hpp:1102</a></div></div>
 <div class="ttc" id="anamespacearmnn_html_a67a0db04d321a74b7e7fcfd3f1a3f70b"><div class="ttname"><a href="namespacearmnn.html#a67a0db04d321a74b7e7fcfd3f1a3f70b">armnn::Status</a></div><div class="ttdeci">Status</div><div class="ttdef"><b>Definition:</b> <a href="_types_8hpp_source.html#l00042">Types.hpp:42</a></div></div>
 <div class="ttc" id="anamespacearmnn_html_a42561b8004ee341ac089d5f1657120db"><div class="ttname"><a href="namespacearmnn.html#a42561b8004ee341ac089d5f1657120db">armnn::NeonUnidirectionalSequenceLstmWorkloadValidate</a></div><div class="ttdeci">arm_compute::Status NeonUnidirectionalSequenceLstmWorkloadValidate(const TensorInfo &amp;input, const TensorInfo &amp;outputStateIn, const TensorInfo &amp;cellStateIn, const TensorInfo &amp;outputStateOut, const TensorInfo &amp;cellStateOut, const TensorInfo &amp;output, const UnidirectionalSequenceLstmDescriptor &amp;descriptor, const LstmInputParamsInfo &amp;paramsInfo)</div><div class="ttdef"><b>Definition:</b> <a href="_neon_unidirectional_sequence_lstm_workload_8cpp_source.html#l00491">NeonUnidirectionalSequenceLstmWorkload.cpp:491</a></div></div>
 <div class="ttc" id="anamespacearmnn_html"><div class="ttname"><a href="namespacearmnn.html">armnn</a></div><div class="ttdoc">Copyright (c) 2021 ARM Limited and Contributors.</div><div class="ttdef"><b>Definition:</b> <a href="01__00__quick__start_8dox_source.html#l00006">01_00_quick_start.dox:6</a></div></div>
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-<div class="ttc" id="astructarmnn_1_1_unidirectional_sequence_lstm_queue_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_unidirectional_sequence_lstm_queue_descriptor.html">armnn::UnidirectionalSequenceLstmQueueDescriptor</a></div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00691">WorkloadData.hpp:691</a></div></div>
+<div class="ttc" id="astructarmnn_1_1_unidirectional_sequence_lstm_queue_descriptor_html"><div class="ttname"><a href="structarmnn_1_1_unidirectional_sequence_lstm_queue_descriptor.html">armnn::UnidirectionalSequenceLstmQueueDescriptor</a></div><div class="ttdef"><b>Definition:</b> <a href="_workload_data_8hpp_source.html#l00696">WorkloadData.hpp:696</a></div></div>
 <div class="ttc" id="aclassarmnn_1_1_neon_base_workload_html"><div class="ttname"><a href="classarmnn_1_1_neon_base_workload.html">armnn::NeonBaseWorkload</a></div><div class="ttdef"><b>Definition:</b> <a href="_neon_base_workload_8hpp_source.html#l00013">NeonBaseWorkload.hpp:13</a></div></div>
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