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| author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2023-11-15 15:42:45 +0000 |
|---|---|---|
| committer | Mike Kelly <mike.kelly@arm.com> | 2023-11-16 15:46:38 +0000 |
| commit | 28ebea470c84c9cf520035ab3ed390675edeb7d9 (patch) | |
| tree | ab53066e7155603faab01a976e5878b2b9f58be4 | |
| parent | 73b152426e4825223b8f2f4963dadbbf942fa130 (diff) | |
| download | armnn-28ebea470c84c9cf520035ab3ed390675edeb7d9.tar.gz | |
IVGCVSW-7937 Review and update documentation related with new operators for 23.11
* GELU added to activation operators, despite not being part of Android NDK
* BROADCAST_TO added to layers, despite not being implemented in any backend
* CAST SIGNED64 added
Change-Id: I32edb9939d28cb997432762e8ea5904f92c12687
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I6a27ebc1233d77522c1bed1c7e89df95e4d55177
| -rw-r--r-- | docs/02_operator_list.dox | 51 |
1 files changed, 47 insertions, 4 deletions
diff --git a/docs/02_operator_list.dox b/docs/02_operator_list.dox index a37b6fa3a7..fa386f21bd 100644 --- a/docs/02_operator_list.dox +++ b/docs/02_operator_list.dox @@ -109,6 +109,7 @@ where N = batches, C = channels, H = height, W = width <li>ANEURALNETWORKS_RELU6 <li>ANEURALNETWORKS_SQRT <li>ANEURALNETWORKS_TANH + <li>GELU </ul> <td>CpuRef <td> @@ -407,6 +408,45 @@ where N = batches, C = channels, H = height, W = width <tr><td>All </table> <tr> + <td rowspan="3">BroadcastToLayer + <td rowspan="3" style="width:200px;"> Layer to broadcast a tensor to a given size. + <td rowspan="3"> + <ul> + <li>N/A + </ul> + <td>CpuRef + <td> + <ul> + <li>N/A + </ul> + <td> + <table> + <tr><th> + <tr><td>N/A + </table> + <tr> + <td>CpuAcc + <td> + <ul> + <li>N/A + </ul> + <td> + <table> + <tr><th> + <tr><td>N/A + </table> + <tr> + <td>GpuAcc + <td> + <ul> + <li>N/A + </ul> + <td> + <table> + <tr><th> + <tr><td>N/A + </table> + <tr> <td rowspan="3">CastLayer <td rowspan="3" style="width:200px;"> Layer to cast a tensor to a type. <td rowspan="3"> @@ -429,6 +469,7 @@ where N = batches, C = channels, H = height, W = width <tr><td>QASYMMU8 <tr><td>QSYMMS16 <tr><td>SIGNED32 + <tr><td>SIGNED64 </table> <tr> <td>CpuAcc @@ -439,11 +480,12 @@ where N = batches, C = channels, H = height, W = width <td> <table> <tr><th> + <tr><td>FLOAT32 + <tr><td>FLOAT16 <tr><td>QASYMMS8 <tr><td>QASYMMU8 - <tr><td>FLOAT16 <tr><td>SIGNED32 - <tr><td>FLOAT32 + <tr><td>SIGNED64 </table> <tr> <td>GpuAcc @@ -454,11 +496,12 @@ where N = batches, C = channels, H = height, W = width <td> <table> <tr><th> + <tr><td>FLOAT32 + <tr><td>FLOAT16 <tr><td>QASYMMS8 <tr><td>QASYMMU8 <tr><td>SIGNED32 - <tr><td>FLOAT16 - <tr><td>FLOAT32 + <tr><td>SIGNED64 </table> <tr> <td rowspan="3">ChannelShuffleLayer |