diff options
Diffstat (limited to 'test/1.2')
| -rw-r--r-- | test/1.2/Capabilities.cpp | 35 | ||||
| -rw-r--r-- | test/1.2/Dilation.cpp | 27 | ||||
| -rw-r--r-- | test/1.2/Lstm.cpp | 83 | ||||
| -rw-r--r-- | test/1.2/Mean.cpp | 204 | ||||
| -rw-r--r-- | test/1.2/UnidirectionalSequenceLstm.cpp | 40 |
5 files changed, 325 insertions, 64 deletions
diff --git a/test/1.2/Capabilities.cpp b/test/1.2/Capabilities.cpp index 15ecf968..41d5ee53 100644 --- a/test/1.2/Capabilities.cpp +++ b/test/1.2/Capabilities.cpp @@ -1,15 +1,12 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // -#include "../../1.2/ArmnnDriverImpl.hpp" - +#include "../DriverTestHelpers.hpp" #include "Utils.h" -#include <armnn/utility/Assert.hpp> - -#include <boost/test/unit_test.hpp> +#include <1.2/ArmnnDriverImpl.hpp> #include <sys/system_properties.h> @@ -62,15 +59,14 @@ void CheckOperandType(const V1_2::Capabilities& capabilities, V1_2::OperandType { using namespace armnn_driver::hal_1_2; V1_0::PerformanceInfo perfInfo = android::nn::lookup(capabilities.operandPerformance, type); - ARMNN_ASSERT(perfInfo.execTime == execTime); - ARMNN_ASSERT(perfInfo.powerUsage == powerUsage); + DOCTEST_CHECK(perfInfo.execTime == execTime); + DOCTEST_CHECK(perfInfo.powerUsage == powerUsage); } -BOOST_FIXTURE_TEST_SUITE(CapabilitiesTests, CapabilitiesFixture) - -BOOST_AUTO_TEST_CASE(PerformanceCapabilitiesWithRuntime) +DOCTEST_TEST_SUITE("CapabilitiesTests") +{ +DOCTEST_TEST_CASE_FIXTURE(CapabilitiesFixture, "PerformanceCapabilitiesWithRuntime") { - using namespace armnn_driver::hal_1_2; using namespace android::nn; auto getCapabilitiesFn = [&](V1_0::ErrorStatus error, const V1_2::Capabilities& capabilities) @@ -94,7 +90,8 @@ BOOST_AUTO_TEST_CASE(PerformanceCapabilitiesWithRuntime) CheckOperandType(capabilities, V1_2::OperandType::OEM, FLT_MAX, FLT_MAX); CheckOperandType(capabilities, V1_2::OperandType::TENSOR_OEM_BYTE, FLT_MAX, FLT_MAX); - ARMNN_ASSERT(error == V1_0::ErrorStatus::NONE); + bool result = (error == V1_0::ErrorStatus::NONE); + DOCTEST_CHECK(result); }; __system_property_set("Armnn.operandTypeTensorFloat32Performance.execTime", "2.0f"); @@ -121,12 +118,11 @@ BOOST_AUTO_TEST_CASE(PerformanceCapabilitiesWithRuntime) armnn::IRuntime::CreationOptions options; armnn::IRuntimePtr runtime(armnn::IRuntime::Create(options)); - ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn); + armnn_driver::hal_1_2::ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn); } -BOOST_AUTO_TEST_CASE(PerformanceCapabilitiesUndefined) +DOCTEST_TEST_CASE_FIXTURE(CapabilitiesFixture, "PerformanceCapabilitiesUndefined") { - using namespace armnn_driver::hal_1_2; using namespace android::nn; float defaultValue = .1f; @@ -155,13 +151,14 @@ BOOST_AUTO_TEST_CASE(PerformanceCapabilitiesUndefined) CheckOperandType(capabilities, V1_2::OperandType::OEM, FLT_MAX, FLT_MAX); CheckOperandType(capabilities, V1_2::OperandType::TENSOR_OEM_BYTE, FLT_MAX, FLT_MAX); - ARMNN_ASSERT(error == V1_0::ErrorStatus::NONE); + bool result = (error == V1_0::ErrorStatus::NONE); + DOCTEST_CHECK(result); }; armnn::IRuntime::CreationOptions options; armnn::IRuntimePtr runtime(armnn::IRuntime::Create(options)); - ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn); + armnn_driver::hal_1_2::ArmnnDriverImpl::getCapabilities_1_2(runtime, getCapabilitiesFn); } -BOOST_AUTO_TEST_SUITE_END()
\ No newline at end of file +}
\ No newline at end of file diff --git a/test/1.2/Dilation.cpp b/test/1.2/Dilation.cpp index 1a7ba4b4..c9182a7c 100644 --- a/test/1.2/Dilation.cpp +++ b/test/1.2/Dilation.cpp @@ -1,17 +1,16 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "../Dilation.hpp" -#include "../../1.2/HalPolicy.hpp" +#include <1.2/HalPolicy.hpp> -#include <boost/test/data/test_case.hpp> - -BOOST_AUTO_TEST_SUITE(DilationTests) +DOCTEST_TEST_SUITE("DilationTests") +{ -BOOST_AUTO_TEST_CASE(ConvolutionExplicitPaddingNoDilation) +DOCTEST_TEST_CASE("ConvolutionExplicitPaddingNoDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = false; @@ -21,7 +20,7 @@ BOOST_AUTO_TEST_CASE(ConvolutionExplicitPaddingNoDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(ConvolutionExplicitPaddingDilation) +DOCTEST_TEST_CASE("ConvolutionExplicitPaddingDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = false; @@ -31,7 +30,7 @@ BOOST_AUTO_TEST_CASE(ConvolutionExplicitPaddingDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(ConvolutionImplicitPaddingNoDilation) +DOCTEST_TEST_CASE("ConvolutionImplicitPaddingNoDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = false; @@ -41,7 +40,7 @@ BOOST_AUTO_TEST_CASE(ConvolutionImplicitPaddingNoDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(ConvolutionImplicitPaddingDilation) +DOCTEST_TEST_CASE("ConvolutionImplicitPaddingDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = false; @@ -51,7 +50,7 @@ BOOST_AUTO_TEST_CASE(ConvolutionImplicitPaddingDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(DepthwiseConvolutionExplicitPaddingNoDilation) +DOCTEST_TEST_CASE("DepthwiseConvolutionExplicitPaddingNoDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = true; @@ -61,7 +60,7 @@ BOOST_AUTO_TEST_CASE(DepthwiseConvolutionExplicitPaddingNoDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(DepthwiseConvolutionExplicitPaddingDilation) +DOCTEST_TEST_CASE("DepthwiseConvolutionExplicitPaddingDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = true; @@ -71,7 +70,7 @@ BOOST_AUTO_TEST_CASE(DepthwiseConvolutionExplicitPaddingDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(DepthwiseConvolutionImplicitPaddingNoDilation) +DOCTEST_TEST_CASE("DepthwiseConvolutionImplicitPaddingNoDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = true; @@ -81,7 +80,7 @@ BOOST_AUTO_TEST_CASE(DepthwiseConvolutionImplicitPaddingNoDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_CASE(DepthwiseConvolutionImplicitPaddingDilation) +DOCTEST_TEST_CASE("DepthwiseConvolutionImplicitPaddingDilation") { DilationTestOptions options; options.m_IsDepthwiseConvolution = true; @@ -91,4 +90,4 @@ BOOST_AUTO_TEST_CASE(DepthwiseConvolutionImplicitPaddingDilation) DilationTestImpl<hal_1_2::HalPolicy>(options); } -BOOST_AUTO_TEST_SUITE_END()
\ No newline at end of file +}
\ No newline at end of file diff --git a/test/1.2/Lstm.cpp b/test/1.2/Lstm.cpp index 03f7fe47..7a2b3942 100644 --- a/test/1.2/Lstm.cpp +++ b/test/1.2/Lstm.cpp @@ -1,51 +1,72 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "../Lstm.hpp" -#include <boost/test/data/test_case.hpp> - -BOOST_AUTO_TEST_SUITE(LstmTests) - using namespace armnn_driver; -BOOST_DATA_TEST_CASE(LstmNoCifgNoPeepholeNoProjectionTest, COMPUTE_DEVICES) +#if defined(ARMNNREF_ENABLED) +DOCTEST_TEST_SUITE("LstmTests_1.2_CpuRef") { - LstmNoCifgNoPeepholeNoProjection<hal_1_2::HalPolicy>(sample); -} -BOOST_DATA_TEST_CASE(LstmCifgPeepholeNoProjectionTest, COMPUTE_DEVICES) -{ - LstmCifgPeepholeNoProjection<hal_1_2::HalPolicy>(sample); -} + DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.2_armnn::Compute::CpuRef") + { + LstmNoCifgNoPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } -BOOST_DATA_TEST_CASE(LstmNoCifgPeepholeProjectionTest, COMPUTE_DEVICES) -{ - LstmNoCifgPeepholeProjection<hal_1_2::HalPolicy>(sample); -} + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.2_CpuRef") + { + LstmCifgPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } -BOOST_DATA_TEST_CASE(LstmCifgPeepholeNoProjectionBatch2Test, COMPUTE_DEVICES) -{ - LstmCifgPeepholeNoProjectionBatch2<hal_1_2::HalPolicy>(sample); -} + DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.2_CpuRef") + { + LstmNoCifgPeepholeProjection<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } -BOOST_DATA_TEST_CASE(LstmNoCifgPeepholeProjectionNoClippingLayerNormTest, COMPUTE_DEVICES) -{ - LstmNoCifgPeepholeProjectionNoClippingLayerNorm<hal_1_2::HalPolicy>(sample); -} + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.2_CpuRef") + { + LstmCifgPeepholeNoProjectionBatch2<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("QuantizedLstmTest_1.2_CpuRef") + { + QuantizedLstm<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } -BOOST_DATA_TEST_CASE(LstmCifgPeepholeProjectionNoClippingLayerNormTest, COMPUTE_DEVICES) -{ - LstmCifgPeepholeProjectionNoClippingLayerNorm<hal_1_2::HalPolicy>(sample); } +#endif #if defined(ARMCOMPUTECL_ENABLED) -BOOST_DATA_TEST_CASE(QuantizedLstmTest, COMPUTE_DEVICES) +DOCTEST_TEST_SUITE("LstmTests_1.2_GpuAcc") { - QuantizedLstm<hal_1_2::HalPolicy>(sample); + + DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.2_GpuAcc") + { + LstmNoCifgNoPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.2_GpuAcc") + { + LstmCifgPeepholeNoProjection<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.2_GpuAcc") + { + LstmNoCifgPeepholeProjection<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.2_GpuAcc") + { + LstmCifgPeepholeNoProjectionBatch2<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("QuantizedLstmTest_1.2_GpuAcc") + { + QuantizedLstm<hal_1_2::HalPolicy>(armnn::Compute::GpuAcc); + } + } #endif - -BOOST_AUTO_TEST_SUITE_END() diff --git a/test/1.2/Mean.cpp b/test/1.2/Mean.cpp new file mode 100644 index 00000000..a2a8b7a1 --- /dev/null +++ b/test/1.2/Mean.cpp @@ -0,0 +1,204 @@ +// +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "../DriverTestHelpers.hpp" +#include "../TestHalfTensor.hpp" + +#include <1.2/HalPolicy.hpp> + +#include <array> + +using Half = half_float::half; + +using namespace android::hardware; +using namespace driverTestHelpers; +using namespace armnn_driver; + +using HalPolicy = hal_1_2::HalPolicy; +using RequestArgument = V1_0::RequestArgument; + +namespace +{ + +void MeanTestImpl(const TestHalfTensor& input, + const hidl_vec<uint32_t>& axisDimensions, + const int32_t* axisValues, + int32_t keepDims, + const TestHalfTensor& expectedOutput, + bool fp16Enabled, + armnn::Compute computeDevice) +{ + auto driver = std::make_unique<ArmnnDriver>(DriverOptions(computeDevice, fp16Enabled)); + + HalPolicy::Model model = {}; + + AddInputOperand<HalPolicy>(model, input.GetDimensions(), V1_2::OperandType::TENSOR_FLOAT16); + + AddTensorOperand<HalPolicy>(model, + axisDimensions, + const_cast<int32_t*>(axisValues), + HalPolicy::OperandType::TENSOR_INT32); + + AddIntOperand<HalPolicy>(model, keepDims); + + AddOutputOperand<HalPolicy>(model, expectedOutput.GetDimensions(), V1_2::OperandType::TENSOR_FLOAT16); + + model.operations.resize(1); + model.operations[0].type = HalPolicy::OperationType::MEAN; + model.operations[0].inputs = hidl_vec<uint32_t>{ 0, 1, 2 }; + model.operations[0].outputs = hidl_vec<uint32_t>{ 3 }; + model.relaxComputationFloat32toFloat16 = fp16Enabled; + + //android::sp<V1_0::IPreparedModel> preparedModel = PrepareModel(model, *driver); + android::sp<V1_2::IPreparedModel> preparedModel = PrepareModel_1_2(model, *driver); + + // The request's memory pools will follow the same order as the inputs + V1_0::DataLocation inLoc = {}; + inLoc.poolIndex = 0; + inLoc.offset = 0; + inLoc.length = input.GetNumElements() * sizeof(Half); + RequestArgument inArg = {}; + inArg.location = inLoc; + inArg.dimensions = input.GetDimensions(); + + // An additional memory pool is needed for the output + V1_0::DataLocation outLoc = {}; + outLoc.poolIndex = 1; + outLoc.offset = 0; + outLoc.length = expectedOutput.GetNumElements() * sizeof(Half); + RequestArgument outArg = {}; + outArg.location = outLoc; + outArg.dimensions = expectedOutput.GetDimensions(); + + // Make the request based on the arguments + V1_0::Request request = {}; + request.inputs = hidl_vec<RequestArgument>{ inArg }; + request.outputs = hidl_vec<RequestArgument>{ outArg }; + + // Set the input data + AddPoolAndSetData(input.GetNumElements(), request, input.GetData()); + + // Add memory for the output + android::sp<IMemory> outMemory = AddPoolAndGetData<Half>(expectedOutput.GetNumElements(), request); + const Half* outputData = static_cast<const Half*>(static_cast<void*>(outMemory->getPointer())); + + if (preparedModel.get() != nullptr) + { + V1_0::ErrorStatus execStatus = Execute(preparedModel, request); + DOCTEST_CHECK((int)execStatus == (int)V1_0::ErrorStatus::NONE); + } + + const Half* expectedOutputData = expectedOutput.GetData(); + for (unsigned int i = 0; i < expectedOutput.GetNumElements(); i++) + { + DOCTEST_CHECK(outputData[i] == expectedOutputData[i]); + } +} + +} // anonymous namespace + +DOCTEST_TEST_SUITE("MeanTests_1.2_CpuRef") +{ + +DOCTEST_TEST_CASE("MeanFp16NoKeepDimsTest_CpuRef") +{ + using namespace half_float::literal; + + TestHalfTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0_h, 2.0_h, 3.0_h, 4.0_h, 5.0_h, 6.0_h, 7.0_h, 8.0_h, 9.0_h, 10.0_h, + 11.0_h, 12.0_h, 13.0_h, 14.0_h, 15.0_h, 16.0_h, 17.0_h, 18.0_h, 19.0_h, + 20.0_h, 21.0_h, 22.0_h, 23.0_h, 24.0_h } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestHalfTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0_h, 13.0_h } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuRef); +} + +DOCTEST_TEST_CASE("MeanFp16KeepDimsTest_CpuRef") +{ + using namespace half_float::literal; + + TestHalfTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0_h, 1.0_h, 2.0_h, 2.0_h, 3.0_h, 3.0_h } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestHalfTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0_h, 2.0_h } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuRef); +} + +} + +#ifdef ARMCOMPUTECL_ENABLED +DOCTEST_TEST_SUITE("MeanTests_1.2_CpuAcc") +{ + DOCTEST_TEST_CASE("MeanFp16NoKeepDimsTest_CpuAcc") + { + using namespace half_float::literal; + + std::vector<Half> in = { 1.0_h, 2.0_h, 3.0_h, 4.0_h, 5.0_h, 6.0_h, 7.0_h, 8.0_h, 9.0_h, 10.0_h, + 11.0_h, 12.0_h, 13.0_h, 14.0_h, 15.0_h, 16.0_h, 17.0_h, 18.0_h, 19.0_h, + 20.0_h, 21.0_h, 22.0_h, 23.0_h, 24.0_h }; + TestHalfTensor input{ armnn::TensorShape{ 4, 3, 2 }, + in}; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + std::vector<Half> out = { 12.0_h, 13.0_h }; + TestHalfTensor expectedOutput{ armnn::TensorShape{ 2 }, out }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuAcc); + } + + DOCTEST_TEST_CASE("MeanFp16KeepDimsTest_CpuAcc") + { + using namespace half_float::literal; + + std::vector<Half> in = { 1.0_h, 1.0_h, 2.0_h, 2.0_h, 3.0_h, 3.0_h }; + TestHalfTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, in }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + std::vector<Half> out = { 2.0_h, 2.0_h }; + TestHalfTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, out }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuAcc); + } +} + +DOCTEST_TEST_SUITE("MeanTests_1.2_GpuAcc") +{ + DOCTEST_TEST_CASE("MeanFp16NoKeepDimsTest_GpuAcc") + { + using namespace half_float::literal; + + TestHalfTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0_h, 2.0_h, 3.0_h, 4.0_h, 5.0_h, 6.0_h, 7.0_h, 8.0_h, 9.0_h, 10.0_h, + 11.0_h, 12.0_h, 13.0_h, 14.0_h, 15.0_h, 16.0_h, 17.0_h, 18.0_h, 19.0_h, + 20.0_h, 21.0_h, 22.0_h, 23.0_h, 24.0_h } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestHalfTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0_h, 13.0_h } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("MeanFp16KeepDimsTest_GpuAcc") + { + using namespace half_float::literal; + + TestHalfTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0_h, 1.0_h, 2.0_h, 2.0_h, 3.0_h, 3.0_h } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestHalfTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0_h, 2.0_h } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::GpuAcc); + } +} +#endif diff --git a/test/1.2/UnidirectionalSequenceLstm.cpp b/test/1.2/UnidirectionalSequenceLstm.cpp new file mode 100644 index 00000000..fd35aa41 --- /dev/null +++ b/test/1.2/UnidirectionalSequenceLstm.cpp @@ -0,0 +1,40 @@ +// +// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "../UnidirectionalSequenceLstm.hpp" + +using namespace armnn_driver; + +DOCTEST_TEST_SUITE("UnidirectionalSequenceLstmTests_1.2_CpuRef") +{ + + DOCTEST_TEST_CASE("UnidirectionalSequenceLstmLayerFloat32Test_1.2_CpuRef") + { + UnidirectionalSequenceLstmLayerFloat32TestImpl<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("UnidirectionalSequenceLstmLayerFloat32TimeMajorTest_1.2_CpuRef") + { + UnidirectionalSequenceLstmLayerFloat32TimeMajorTestImpl<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("UnidirectionalSequenceLstmLayerNoCifgWithPeepholeWithProjectionTest_1.2_CpuRef") + { + UnidirectionalSequenceLstmLayerNoCifgWithPeepholeWithProjectionTestImpl<hal_1_2::HalPolicy> + (armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("UnidirectionalSequenceLstmLayerNoCifgWithPeepholeWithProjectionWithLayerNormTest_1.2_CpuRef") + { + UnidirectionalSequenceLstmLayerNoCifgWithPeepholeWithProjectionWithLayerNormTestImpl<hal_1_2::HalPolicy> + (armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("UnidirectionalSequenceLstmWithCifgWithPeepholeNoProjectionTest_1.2_CpuRef") + { + UnidirectionalSequenceLstmWithCifgWithPeepholeNoProjectionTestImpl<hal_1_2::HalPolicy>(armnn::Compute::CpuRef); + } + +}
\ No newline at end of file |