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-rw-r--r--src/common/cpuinfo/CpuInfo.cpp20
-rw-r--r--src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp2
-rw-r--r--src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp2
-rw-r--r--src/core/NEON/kernels/arm_gemm/transform.cpp2
-rw-r--r--src/cpu/CpuContext.cpp4
-rw-r--r--src/runtime/CPP/CPPScheduler.cpp4
6 files changed, 20 insertions, 14 deletions
diff --git a/src/common/cpuinfo/CpuInfo.cpp b/src/common/cpuinfo/CpuInfo.cpp
index b96e108af5..2b85375654 100644
--- a/src/common/cpuinfo/CpuInfo.cpp
+++ b/src/common/cpuinfo/CpuInfo.cpp
@@ -40,13 +40,13 @@
#include <unordered_map>
#endif /* !defined(BARE_METAL) */
-#if !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
+#if !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__))
#include <asm/hwcap.h> /* Get HWCAP bits from asm/hwcap.h */
#include <sys/auxv.h>
#elif defined(__APPLE__) && defined(__aarch64__)
#include <sys/sysctl.h>
#include <sys/types.h>
-#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */
+#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
#define ARM_COMPUTE_CPU_FEATURE_HWCAP_CPUID (1 << 11)
#define ARM_COMPUTE_GET_FEATURE_REG(var, freg) __asm __volatile("MRS %0, " #freg \
@@ -57,7 +57,7 @@ namespace cpuinfo
{
namespace
{
-#if !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
+#if !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__))
/** Extract MIDR using CPUID information that are exposed to user-space
*
* @param[in] max_num_cpus Maximum number of possible CPUs
@@ -273,7 +273,7 @@ int get_hw_capability(const std::string& cap)
sysctlbyname(cap.c_str(), &result, &size, NULL, 0);
return result;
}
-#endif /* defined(__aarch64__) && defined(__APPLE__) */
+#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
#if defined(BARE_METAL) && defined(__aarch64__)
uint64_t get_sve_feature_reg()
@@ -297,7 +297,7 @@ CpuInfo::CpuInfo(CpuIsaInfo isa, std::vector<CpuModel> cpus)
CpuInfo CpuInfo::build()
{
-#if !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__))
+#if !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__))
const uint32_t hwcaps = getauxval(AT_HWCAP);
const uint32_t hwcaps2 = getauxval(AT_HWCAP2);
const uint32_t max_cpus = get_max_cpus();
@@ -328,7 +328,7 @@ CpuInfo CpuInfo::build()
CpuInfo info(isa, cpus_model);
return info;
-#elif(BARE_METAL) && defined(__aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */
+#elif(BARE_METAL) && defined(__aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
// Assume single CPU in bare metal mode. Just read the ID register and feature bits directly.
uint64_t isar0 = 0, isar1 = 0, pfr0 = 0, svefr0 = 0, midr = 0;
@@ -357,7 +357,7 @@ CpuInfo CpuInfo::build()
#else /* #elif defined(__aarch64__) && defined(__APPLE__) */
CpuInfo info(CpuIsaInfo(), { CpuModel::GENERIC });
return info;
-#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */
+#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */
}
CpuModel CpuInfo::cpu_model(uint32_t cpuid) const
@@ -371,11 +371,11 @@ CpuModel CpuInfo::cpu_model(uint32_t cpuid) const
CpuModel CpuInfo::cpu_model() const
{
-#if defined(BARE_METAL) || defined(__APPLE__) || (!defined(__arm__) && !defined(__aarch64__))
+#if defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__))
return cpu_model(0);
-#else /* defined(BARE_METAL) || defined(__APPLE__) || (!defined(__arm__) && !defined(__aarch64__)) */
+#else /* defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) */
return cpu_model(sched_getcpu());
-#endif /* defined(BARE_METAL) || defined(__APPLE__) || (!defined(__arm__) && !defined(__aarch64__)) */
+#endif /* defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) */
}
uint32_t CpuInfo::num_cpus() const
diff --git a/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp b/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp
index 20c8230148..79fc65e561 100644
--- a/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp
+++ b/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp
@@ -23,7 +23,9 @@
*/
#pragma once
+#if !defined(__OpenBSD__)
#include <alloca.h>
+#endif /* !defined(__OpenBSD__) */
#include <algorithm>
#include <cassert>
diff --git a/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp b/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp
index d5003e4a19..91988e8c33 100644
--- a/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp
+++ b/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp
@@ -28,7 +28,9 @@
#include "interleave_indirect.hpp"
#include "bfloat.hpp"
+#if !defined(__OpenBSD__)
#include <alloca.h>
+#endif /* !defined(__OpenBSD__) */
#include <algorithm>
#include <cstddef>
diff --git a/src/core/NEON/kernels/arm_gemm/transform.cpp b/src/core/NEON/kernels/arm_gemm/transform.cpp
index 60376ab80b..c6a3bc0edb 100644
--- a/src/core/NEON/kernels/arm_gemm/transform.cpp
+++ b/src/core/NEON/kernels/arm_gemm/transform.cpp
@@ -25,7 +25,9 @@
#include "bfloat.hpp"
+#if !defined(__OpenBSD__)
#include <alloca.h>
+#endif /* !defined(__OpenBSD__) */
namespace arm_gemm {
diff --git a/src/cpu/CpuContext.cpp b/src/cpu/CpuContext.cpp
index 917bf68a0c..0cc5070917 100644
--- a/src/cpu/CpuContext.cpp
+++ b/src/cpu/CpuContext.cpp
@@ -28,9 +28,9 @@
#include "src/cpu/CpuTensor.h"
#include <cstdlib>
-#if !defined(__APPLE__)
+#if !defined(__APPLE__) && !defined(__OpenBSD__)
#include <malloc.h>
-#endif // !defined(__APPLE__)
+#endif // !defined(__APPLE__) && !defined(__OpenBSD__)
namespace arm_compute
diff --git a/src/runtime/CPP/CPPScheduler.cpp b/src/runtime/CPP/CPPScheduler.cpp
index 3d7f1f16b1..94a2f31d64 100644
--- a/src/runtime/CPP/CPPScheduler.cpp
+++ b/src/runtime/CPP/CPPScheduler.cpp
@@ -104,12 +104,12 @@ void set_thread_affinity(int core_id)
return;
}
-#if !defined(__APPLE__)
+#if !defined(__APPLE__) && !defined(__OpenBSD__)
cpu_set_t set;
CPU_ZERO(&set);
CPU_SET(core_id, &set);
ARM_COMPUTE_EXIT_ON_MSG(sched_setaffinity(0, sizeof(set), &set), "Error setting thread affinity");
-#endif /* !defined(__APPLE__) */
+#endif /* !defined(__APPLE__) && !defined(__OpenBSD__) */
}
/** There are currently 2 scheduling modes supported by CPPScheduler
generated by cgit v1.2.1 (git 2.23.0) at 2024-07-07 14:52:46 +0000