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-rw-r--r--src/core/CL/cl_kernels/nhwc/batch_to_space.cl8
-rw-r--r--src/core/CL/cl_kernels/nhwc/depth_to_space.cl6
-rw-r--r--src/core/CL/cl_kernels/nhwc/space_to_batch.cl8
-rw-r--r--src/core/CL/cl_kernels/nhwc/space_to_depth.cl6
4 files changed, 14 insertions, 14 deletions
diff --git a/src/core/CL/cl_kernels/nhwc/batch_to_space.cl b/src/core/CL/cl_kernels/nhwc/batch_to_space.cl
index 16141bcd2e..b910a753a6 100644
--- a/src/core/CL/cl_kernels/nhwc/batch_to_space.cl
+++ b/src/core/CL/cl_kernels/nhwc/batch_to_space.cl
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, 2023 Arm Limited.
+ * Copyright (c) 2018-2021, 2023-2024 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -63,7 +63,7 @@ __kernel void batch_to_space_nhwc(
TENSOR3D_DECLARATION(output))
{
Tensor3D out = CONVERT_TO_TENSOR3D_STRUCT(output);
- Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input, 0);
+ Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input);
Vector block = CONVERT_TO_VECTOR_STRUCT_NO_STEP(block_shape);
const int block_x = *((__global int *)vector_offset(&block, 0));
@@ -113,7 +113,7 @@ __kernel void batch_to_space_static_nhwc(
TENSOR3D_DECLARATION(output))
{
Tensor3D out = CONVERT_TO_TENSOR3D_STRUCT(output);
- Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input, 0);
+ Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input);
const int block_x = BLOCK_SHAPE_X;
const int block_y = BLOCK_SHAPE_Y;
@@ -128,4 +128,4 @@ __kernel void batch_to_space_static_nhwc(
*((__global DATA_TYPE *)out.ptr) = *((__global DATA_TYPE *)tensor4D_offset(&in, z, in_x, in_y, in_batch));
}
-#endif // defined(DATA_TYPE) && defined(BATCH_SIZE) && defined(BLOCK_SHAPE_X) && defined(BLOCK_SHAPE_Y) \ No newline at end of file
+#endif // defined(DATA_TYPE) && defined(BATCH_SIZE) && defined(BLOCK_SHAPE_X) && defined(BLOCK_SHAPE_Y)
diff --git a/src/core/CL/cl_kernels/nhwc/depth_to_space.cl b/src/core/CL/cl_kernels/nhwc/depth_to_space.cl
index 5464a4bef8..84f8aa7263 100644
--- a/src/core/CL/cl_kernels/nhwc/depth_to_space.cl
+++ b/src/core/CL/cl_kernels/nhwc/depth_to_space.cl
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021 Arm Limited.
+ * Copyright (c) 2019-2021, 2024 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -54,7 +54,7 @@ __kernel void depth_to_space_nhwc(
TENSOR4D_DECLARATION(output))
{
Tensor3D in = CONVERT_TO_TENSOR3D_STRUCT(input);
- Tensor4D out = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(output, 0);
+ Tensor4D out = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(output);
const int r = (CHANNEL_SIZE / (BLOCK_SHAPE * BLOCK_SHAPE));
const int x = get_global_id(1);
@@ -66,4 +66,4 @@ __kernel void depth_to_space_nhwc(
*((__global DATA_TYPE *)tensor4D_offset(&out, z, out_x, out_y, batch_id)) = *((__global DATA_TYPE *)in.ptr);
}
-#endif // defined(DATA_TYPE) && defined(BLOCK_SHAPE) && defined(CHANNEL_SIZE) \ No newline at end of file
+#endif // defined(DATA_TYPE) && defined(BLOCK_SHAPE) && defined(CHANNEL_SIZE)
diff --git a/src/core/CL/cl_kernels/nhwc/space_to_batch.cl b/src/core/CL/cl_kernels/nhwc/space_to_batch.cl
index 785206e3b9..695bd4c217 100644
--- a/src/core/CL/cl_kernels/nhwc/space_to_batch.cl
+++ b/src/core/CL/cl_kernels/nhwc/space_to_batch.cl
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021 Arm Limited.
+ * Copyright (c) 2018-2021, 2024 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -64,7 +64,7 @@ __kernel void space_to_batch_nhwc(
const int batch_id,
TENSOR3D_DECLARATION(output))
{
- Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input, 0);
+ Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input);
Image pad = CONVERT_TO_IMAGE_STRUCT_NO_STEP(paddings);
Vector block = CONVERT_TO_VECTOR_STRUCT_NO_STEP(block_shape);
Tensor3D out = CONVERT_TO_TENSOR3D_STRUCT(output);
@@ -130,7 +130,7 @@ __kernel void space_to_batch_static_nhwc(
const int batch_id,
TENSOR3D_DECLARATION(output))
{
- Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input, 0);
+ Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input);
Tensor3D out = CONVERT_TO_TENSOR3D_STRUCT(output);
int block_x = BLOCK_SHAPE_X;
@@ -152,4 +152,4 @@ __kernel void space_to_batch_static_nhwc(
*((__global DATA_TYPE *)out.ptr) = *((__global DATA_TYPE *)tensor4D_offset(&in, z, in_x, in_y, w));
}
}
-#endif // defined(BATCH_SIZE) && defined(DATA_TYPE) && defined(BLOCK_SHAPE_X) && defined(BLOCK_SHAPE_Y) && defined(PAD_LEFT_X) && defined(PAD_RIGHT_X) && defined(PAD_LEFT_Y) && defined(PAD_RIGHT_Y) && defined(WIDTH_IN) && defined(HEIGHT_IN) \ No newline at end of file
+#endif // defined(BATCH_SIZE) && defined(DATA_TYPE) && defined(BLOCK_SHAPE_X) && defined(BLOCK_SHAPE_Y) && defined(PAD_LEFT_X) && defined(PAD_RIGHT_X) && defined(PAD_LEFT_Y) && defined(PAD_RIGHT_Y) && defined(WIDTH_IN) && defined(HEIGHT_IN)
diff --git a/src/core/CL/cl_kernels/nhwc/space_to_depth.cl b/src/core/CL/cl_kernels/nhwc/space_to_depth.cl
index d44e78d990..10aac6d5fb 100644
--- a/src/core/CL/cl_kernels/nhwc/space_to_depth.cl
+++ b/src/core/CL/cl_kernels/nhwc/space_to_depth.cl
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021 Arm Limited.
+ * Copyright (c) 2019-2021, 2024 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -53,7 +53,7 @@ __kernel void space_to_depth_nhwc(
const int batch_id,
TENSOR3D_DECLARATION(output))
{
- Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input, 0);
+ Tensor4D in = CONVERT_TO_TENSOR4D_STRUCT_NO_STEP(input);
Tensor3D out = CONVERT_TO_TENSOR3D_STRUCT(output);
const int r = (CHANNEL_SIZE / (BLOCK_SHAPE * BLOCK_SHAPE));
@@ -66,4 +66,4 @@ __kernel void space_to_depth_nhwc(
*((__global DATA_TYPE *)out.ptr) = *((__global DATA_TYPE *)tensor4D_offset(&in, z, in_x, in_y, batch_id));
}
-#endif // defined(DATA_TYPE) && defined(BLOCK_SHAPE) && defined(CHANNEL_SIZE) \ No newline at end of file
+#endif // defined(DATA_TYPE) && defined(BLOCK_SHAPE) && defined(CHANNEL_SIZE)