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authorMatthew Bentham <Matthew.Bentham@arm.com>2023-05-30 13:35:34 +0000
committerMatthew Bentham <matthew.bentham@arm.com>2023-06-15 11:22:29 +0000
commitf1aeab9cfb6e9a2a5a16ed79bf341ad11c555233 (patch)
tree1dad30483ae919a0645e5ccec5d51a29da16a1b4 /src/cpu/operators
parentbec9b032ddcff449c7ad40febbcab24c23ee58a0 (diff)
downloadComputeLibrary-f1aeab9cfb6e9a2a5a16ed79bf341ad11c555233.tar.gz
Break up arm_compute/core/Types.h a bit
Split some of the larger types with inlined code into their own header files, so that the implementation of them needn't be included everywhere. Change-Id: Id3ec2d42efbd33cedb55705a5a24e1b90c8b7a01 Signed-off-by: Matthew Bentham <Matthew.Bentham@arm.com> Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/524782 Tested-by: bsgcomp <bsgcomp@arm.com> Reviewed-by: Gunes Bayir <gunes.bayir@arm.com> Comments-Addressed: bsgcomp <bsgcomp@arm.com> Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9757 Tested-by: Arm Jenkins <bsgcomp@arm.com> Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com> Reviewed-by: Jakub Sujak <jakub.sujak@arm.com> Comments-Addressed: Arm Jenkins <bsgcomp@arm.com> Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/operators')
-rw-r--r--src/cpu/operators/CpuAdd.h3
-rw-r--r--src/cpu/operators/CpuConv2d.h3
-rw-r--r--src/cpu/operators/CpuDepthwiseConv2dAssemblyDispatch.h4
-rw-r--r--src/cpu/operators/CpuFullyConnected.h1
-rw-r--r--src/cpu/operators/CpuGemm.h1
-rw-r--r--src/cpu/operators/CpuGemmConv2d.h3
-rw-r--r--src/cpu/operators/CpuGemmLowpMatrixMultiplyCore.h3
-rw-r--r--src/cpu/operators/CpuMul.h5
-rw-r--r--src/cpu/operators/CpuSub.h5
-rw-r--r--src/cpu/operators/internal/CpuGemmAssemblyDispatch.h1
10 files changed, 20 insertions, 9 deletions
diff --git a/src/cpu/operators/CpuAdd.h b/src/cpu/operators/CpuAdd.h
index 4ad6d7fe65..17bac81460 100644
--- a/src/cpu/operators/CpuAdd.h
+++ b/src/cpu/operators/CpuAdd.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022 Arm Limited.
+ * Copyright (c) 2021-2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -24,6 +24,7 @@
#ifndef ARM_COMPUTE_CPU_ADD_H
#define ARM_COMPUTE_CPU_ADD_H
+#include "arm_compute/core/ActivationLayerInfo.h"
#include "src/cpu/ICpuOperator.h"
namespace arm_compute
diff --git a/src/cpu/operators/CpuConv2d.h b/src/cpu/operators/CpuConv2d.h
index daf068f361..7fefe63403 100644
--- a/src/cpu/operators/CpuConv2d.h
+++ b/src/cpu/operators/CpuConv2d.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited.
+ * Copyright (c) 2017-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -21,6 +21,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
+#include "arm_compute/core/ActivationLayerInfo.h"
#include "src/core/common/Macros.h"
#include "src/cpu/ICpuOperator.h"
diff --git a/src/cpu/operators/CpuDepthwiseConv2dAssemblyDispatch.h b/src/cpu/operators/CpuDepthwiseConv2dAssemblyDispatch.h
index af202ced5b..baa301b724 100644
--- a/src/cpu/operators/CpuDepthwiseConv2dAssemblyDispatch.h
+++ b/src/cpu/operators/CpuDepthwiseConv2dAssemblyDispatch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021 Arm Limited.
+ * Copyright (c) 2019-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -29,6 +29,8 @@
namespace arm_compute
{
+struct ConvolutionInfo;
+
namespace cpu
{
/** Depthwise convolution assembly kernel glue */
diff --git a/src/cpu/operators/CpuFullyConnected.h b/src/cpu/operators/CpuFullyConnected.h
index a5a464f67a..db8d71d89e 100644
--- a/src/cpu/operators/CpuFullyConnected.h
+++ b/src/cpu/operators/CpuFullyConnected.h
@@ -26,6 +26,7 @@
#include "src/cpu/ICpuOperator.h"
+#include "arm_compute/core/FullyConnectedLayerInfo.h"
#include "arm_compute/core/TensorInfo.h"
#include <memory>
diff --git a/src/cpu/operators/CpuGemm.h b/src/cpu/operators/CpuGemm.h
index bc8adaec32..20d516cbcb 100644
--- a/src/cpu/operators/CpuGemm.h
+++ b/src/cpu/operators/CpuGemm.h
@@ -26,6 +26,7 @@
#include "src/cpu/ICpuOperator.h"
+#include "arm_compute/core/GEMMInfo.h"
#include "arm_compute/core/ITensorPack.h"
#include "arm_compute/core/TensorInfo.h"
#include "arm_compute/core/Types.h"
diff --git a/src/cpu/operators/CpuGemmConv2d.h b/src/cpu/operators/CpuGemmConv2d.h
index 08b76a6c46..1739ea6103 100644
--- a/src/cpu/operators/CpuGemmConv2d.h
+++ b/src/cpu/operators/CpuGemmConv2d.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022 Arm Limited.
+ * Copyright (c) 2021-2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -24,6 +24,7 @@
#ifndef ARM_COMPUTE_CPU_GEMM_CONV2D_H
#define ARM_COMPUTE_CPU_GEMM_CONV2D_H
+#include "arm_compute/core/ActivationLayerInfo.h"
#include "arm_compute/core/TensorInfo.h"
#include "arm_compute/core/Types.h"
#include "src/cpu/ICpuOperator.h"
diff --git a/src/cpu/operators/CpuGemmLowpMatrixMultiplyCore.h b/src/cpu/operators/CpuGemmLowpMatrixMultiplyCore.h
index a7f62aeaa9..5914d11ded 100644
--- a/src/cpu/operators/CpuGemmLowpMatrixMultiplyCore.h
+++ b/src/cpu/operators/CpuGemmLowpMatrixMultiplyCore.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited.
+ * Copyright (c) 2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -24,6 +24,7 @@
#ifndef ARM_COMPUTE_CPU_GEMMLOWP_MATRIXMULTIPLY_CORE_H
#define ARM_COMPUTE_CPU_GEMMLOWP_MATRIXMULTIPLY_CORE_H
+#include "arm_compute/core/GEMMInfo.h"
#include "arm_compute/core/TensorInfo.h"
#include "src/core/common/Macros.h"
#include "src/cpu/ICpuOperator.h"
diff --git a/src/cpu/operators/CpuMul.h b/src/cpu/operators/CpuMul.h
index 576a357d42..01c81bcb7b 100644
--- a/src/cpu/operators/CpuMul.h
+++ b/src/cpu/operators/CpuMul.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2021 Arm Limited.
+ * Copyright (c) 2016-2021, 2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -24,6 +24,7 @@
#ifndef ARM_COMPUTE_CPU_MUL_H
#define ARM_COMPUTE_CPU_MUL_H
+#include "arm_compute/core/ActivationLayerInfo.h"
#include "arm_compute/core/ITensorInfo.h"
#include "src/cpu/ICpuOperator.h"
@@ -102,4 +103,4 @@ public:
};
} // namespace cpu
} // namespace arm_compute
-#endif /* ARM_COMPUTE_CPU_MUL_H */ \ No newline at end of file
+#endif /* ARM_COMPUTE_CPU_MUL_H */
diff --git a/src/cpu/operators/CpuSub.h b/src/cpu/operators/CpuSub.h
index d463d1e063..ceae3e9c11 100644
--- a/src/cpu/operators/CpuSub.h
+++ b/src/cpu/operators/CpuSub.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022 Arm Limited.
+ * Copyright (c) 2021-2023 Arm Limited.
*
* SPDX-License-Identifier: MIT
*
@@ -24,6 +24,7 @@
#ifndef ARM_COMPUTE_CPU_SUB_H
#define ARM_COMPUTE_CPU_SUB_H
+#include "arm_compute/core/ActivationLayerInfo.h"
#include "src/cpu/ICpuOperator.h"
namespace arm_compute
@@ -66,4 +67,4 @@ public:
};
} // namespace cpu
} // namespace arm_compute
-#endif /* ARM_COMPUTE_CPU_SUB_H */ \ No newline at end of file
+#endif /* ARM_COMPUTE_CPU_SUB_H */
diff --git a/src/cpu/operators/internal/CpuGemmAssemblyDispatch.h b/src/cpu/operators/internal/CpuGemmAssemblyDispatch.h
index 588c45294a..66c3223a4e 100644
--- a/src/cpu/operators/internal/CpuGemmAssemblyDispatch.h
+++ b/src/cpu/operators/internal/CpuGemmAssemblyDispatch.h
@@ -24,6 +24,7 @@
#ifndef ARM_COMPUTE_CPU_INTERNAL_CPU_GEMM_ASSEMBLY_DISPATCH_H
#define ARM_COMPUTE_CPU_INTERNAL_CPU_GEMM_ASSEMBLY_DISPATCH_H
+#include "arm_compute/core/ActivationLayerInfo.h"
#include "src/core/common/Macros.h"
#include "src/cpu/ICpuOperator.h"