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| author | Gunes Bayir <gunes.bayir@arm.com> | 2024-07-05 20:31:29 +0100 |
|---|---|---|
| committer | Gunes Bayir <gunes.bayir@arm.com> | 2024-07-11 10:11:57 +0000 |
| commit | a37d6372946b6bdc07ffe1dddfd4fcf2d8438e47 (patch) | |
| tree | e90b174d71b0e543cf15c2b31f6a9bac8bf6ed6c /src/cpu/kernels/CpuDirectConv3dKernel.cpp | |
| parent | 8dc9b944a471f50403efa46924aa8b9de35cf838 (diff) | |
| download | ComputeLibrary-a37d6372946b6bdc07ffe1dddfd4fcf2d8438e47.tar.gz | |
test: Enable Fp16 tests in Multi-ISA build for Conv3D
Partially Resolves: COMPMID-7185
Change-Id: I437daf3a65b22e065828f3ada6ef3dac9d8c7357
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/11854
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Ramy Elgammal <ramy.elgammal@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/kernels/CpuDirectConv3dKernel.cpp')
| -rw-r--r-- | src/cpu/kernels/CpuDirectConv3dKernel.cpp | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/src/cpu/kernels/CpuDirectConv3dKernel.cpp b/src/cpu/kernels/CpuDirectConv3dKernel.cpp index b5b2aed1ba..9c37ece3dd 100644 --- a/src/cpu/kernels/CpuDirectConv3dKernel.cpp +++ b/src/cpu/kernels/CpuDirectConv3dKernel.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2022 Arm Limited. + * Copyright (c) 2021-2022, 2024 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -25,8 +25,8 @@ #include "arm_compute/core/Error.h" #include "arm_compute/core/Helpers.h" -#include "arm_compute/core/IAccessWindow.h" #include "arm_compute/core/ITensor.h" +#include "arm_compute/core/Steps.h" #include "arm_compute/core/Types.h" #include "arm_compute/core/Utils.h" #include "arm_compute/core/utils/misc/ShapeCalculator.h" @@ -35,10 +35,8 @@ #include "src/core/common/Registrars.h" #include "src/core/CPP/Validate.h" #include "src/core/helpers/AutoConfiguration.h" -#include "src/core/NEON/wrapper/wrapper.h" -#include "src/cpu/kernels/conv3d/neon/list.h" - -#include <algorithm> +#include "src/core/helpers/WindowHelpers.h" +#include "src/cpu/kernels/conv3d/list.h" using namespace arm_compute::detail; @@ -51,18 +49,16 @@ namespace kernels namespace { static const std::vector<CpuDirectConv3dKernel::DirectConv3dKernel> available_kernels = { -#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) {"neon_fp16_directconv3d", [](const DataTypeISASelectorData &data) { return data.dt == DataType::F16 && data.isa.fp16; }, - REGISTER_FP16_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float16_t>)}, -#endif /* !defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) */ + REGISTER_FP16_NEON(directconv3d_fp16_neon_ndhwc)}, {"neon_fp32_directconv3d", [](const DataTypeISASelectorData &data) { return data.dt == DataType::F32; }, - REGISTER_FP32_NEON(arm_compute::cpu::directconv3d_float_neon_ndhwc<float>)}, + REGISTER_FP32_NEON(directconv3d_fp32_neon_ndhwc)}, {"neon_qasymm8_directconv3d", [](const DataTypeISASelectorData &data) { return data.dt == DataType::QASYMM8; }, - REGISTER_QASYMM8_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<uint8_t>)}, + REGISTER_QASYMM8_NEON(directconv3d_qu8_neon_ndhwc)}, {"neon_qasymm8_signed_directconv3d", [](const DataTypeISASelectorData &data) { return data.dt == DataType::QASYMM8_SIGNED; }, - REGISTER_QASYMM8_SIGNED_NEON(arm_compute::cpu::directconv3d_quantized_neon_ndhwc<int8_t>)}}; + REGISTER_QASYMM8_SIGNED_NEON(directconv3d_qs8_neon_ndhwc)}}; Status validate_arguments(const ITensorInfo *src0, const ITensorInfo *src1, |