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| author | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-02-02 14:59:09 +0000 |
|---|---|---|
| committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-02-04 17:43:55 +0000 |
| commit | cf87f509fc23d02c56569f794a3fb59e1b8be277 (patch) | |
| tree | 0fe55158f2065dc6a314e82935558b9748165285 /src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp | |
| parent | 89de118ccbebd5a943634137d0c160d4867da49c (diff) | |
| download | ComputeLibrary-cf87f509fc23d02c56569f794a3fb59e1b8be277.tar.gz | |
Tweak scheduling use of SQDMULH in quantized AVG pooling
Resolves COMPMID-4195
Change-Id: Ie5116c1ddddccafba40432fd4b5245bb27890a88
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4997
Reviewed-by: TeresaARM <teresa.charlinreyes@arm.com>
Reviewed-by: Manuel Bottini <manuel.bottini@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp')
| -rw-r--r-- | src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp index 0f377d90a0..f6e23215b8 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst/generic.cpp @@ -65,13 +65,13 @@ void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( __asm__ __volatile__( "ldr x14, [%x[args], %[offsetof_n_channels]]\n" "ptrue p2.b\n" - "ldr x19, [%x[args], %[offsetof_outptrs]]\n" + "ldr x20, [%x[args], %[offsetof_outptrs]]\n" "mov x13, #0x0\n" + "ldr x19, [%x[args], %[offsetof_inptrs]]\n" "mov x12, #0x0\n" - "ldp x11, x10, [x19, #0x0]\n" + "ldp x11, x10, [x20, #0x0]\n" "whilelt p1.h, x13, x14\n" - "ldp x9, x28, [x19, #0x10]\n" - "ldr x19, [%x[args], %[offsetof_inptrs]]\n" + "ldp x9, x28, [x20, #0x10]\n" "ldp x27, x26, [x19, #0x0]\n" "ldp x25, x24, [x19, #0x10]\n" "ldp x23, x22, [x19, #0x20]\n" @@ -105,9 +105,9 @@ void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "ld1h { z26.h }, p1/Z, [x22, x13, LSL #1]\n" "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z18.h\n" "ld1h { z25.h }, p1/Z, [x25, x13, LSL #1]\n" - "movprfx z18, z17\n fmax z18.h, p2/M, z18.h, z22.h\n" + "movprfx z18, z22\n fmax z18.h, p2/M, z18.h, z17.h\n" "ld1h { z24.h }, p1/Z, [x21, x13, LSL #1]\n" - "movprfx z17, z16\n fmax z17.h, p2/M, z17.h, z21.h\n" + "movprfx z17, z21\n fmax z17.h, p2/M, z17.h, z16.h\n" "ld1h { z23.h }, p1/Z, [x19, x13, LSL #1]\n" "incw x13\n" "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z20.h\n" @@ -128,8 +128,8 @@ void sve_fp16_nhwc_max_2x2_s1_output2x2_depthfirst_impl( "movprfx z20, z26\n fmax z20.h, p2/M, z20.h, z23.h\n" "movprfx z19, z22\n fmax z19.h, p2/M, z19.h, z18.h\n" "st1h { z19.h }, p0, [x11, x12, LSL #1]\n" - "movprfx z18, z17\n fmax z18.h, p2/M, z18.h, z22.h\n" - "movprfx z17, z16\n fmax z17.h, p2/M, z17.h, z21.h\n" + "movprfx z18, z22\n fmax z18.h, p2/M, z18.h, z17.h\n" + "movprfx z17, z21\n fmax z17.h, p2/M, z17.h, z16.h\n" "st1h { z18.h }, p0, [x10, x12, LSL #1]\n" "movprfx z16, z21\n fmax z16.h, p2/M, z16.h, z20.h\n" "st1h { z17.h }, p0, [x9, x12, LSL #1]\n" |