From cb7e029f460d7b826283011954722af16cbb9e91 Mon Sep 17 00:00:00 2001 From: Won Jeon Date: Wed, 28 Jun 2023 22:34:38 +0000 Subject: Fix logical right shift operator for signed negative integers The issue reported from https://jira.arm.com/browse/MLTOSA-688 Signed-off-by: Won Jeon Change-Id: Id37100ba8bc2ac64b1f54788c6f765fedfab0816 --- reference_model/src/ops/ewise_binary.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/reference_model/src/ops/ewise_binary.cc b/reference_model/src/ops/ewise_binary.cc index c697db0..57eab5f 100644 --- a/reference_model/src/ops/ewise_binary.cc +++ b/reference_model/src/ops/ewise_binary.cc @@ -327,21 +327,21 @@ int OpLogicalRightShift::register_fcn() this->fcn = [this](InEigenType a, InEigenType b) -> OutEigenType { REQUIRE(b >= 0 && b <= 31, "OpLogicalRightShift: shift value %d is out of valid range [0, 31]", (int32_t)b); - return static_cast(static_cast(a) >> b); + return static_cast(static_cast(static_cast(a) >> b)); }; break; case DType_INT16: this->fcn = [this](InEigenType a, InEigenType b) -> OutEigenType { REQUIRE(b >= 0 && b <= 31, "OpLogicalRightShift: shift value %d is out of valid range [0, 31]", (int32_t)b); - return static_cast(static_cast(a) >> b); + return static_cast(static_cast(static_cast(a) >> b)); }; break; case DType_INT32: this->fcn = [this](InEigenType a, InEigenType b) -> OutEigenType { REQUIRE(b >= 0 && b <= 31, "OpLogicalRightShift: shift value %d is out of valid range [0, 31]", (int32_t)b); - return static_cast(static_cast(a) >> b); + return static_cast(static_cast(static_cast(a) >> b)); }; break; default: -- cgit v1.2.1