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2023-02-28Update rank limits for SLICE, TILE and TRANSPOSELuke Hutton
Updated to align with corresponding changes to the spec. In addition, some ERROR_IF tests have been updated to match the checks specified by the spec, including: PAD, SLICE, TILE, TRANSPOSE. Signed-off-by: Luke Hutton <luke.hutton@arm.com> Change-Id: Ie2c5f48e79a5610eb82739170e25057a63dac1d8
2023-02-10Add FFT2d to the reference modelLuke Hutton
Includes: * FFT2d reference implementation * Basic TOSA tests Change-Id: Ie79fcb713542345d550ec013646810c1e890e388 Signed-off-by: Luke Hutton <luke.hutton@arm.com>
2023-02-02Remove accumulator attributes from all but AVG_POOL2DJames Ward
Signed-off-by: James Ward <james.ward@arm.com> Change-Id: If67f503a1848967bc1671646c3011d055b622c52
2023-01-31Create MI tests for Type Conversion: CASTJames Ward
* Add exclusion regex's to conformance generation Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I15bef7451efd5662065060242d35bd7fa3381487
2023-01-24Add RFFT2d to the reference modelLuke Hutton
Includes: * RFFT2d reference implementation * TFLite framework tests * Basic TOSA tests * Serialization submodule upgrade with support for FFT/RFFT Signed-off-by: Luke Hutton <luke.hutton@arm.com> Change-Id: I2a687e9cf87fb62a26160ea52439ba9830bea36e
2023-01-19Fix for sign extending LOGICAL LEFT/RIGHT SHIFT resultsJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I04261178694c004409aef2ff5c84c32b04729433
2023-01-19Create MI tests for Activation: CLAMP; Data Layout: PADJames Ward
* Existing float attributes now serialized as bytes Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I415276706b9daf0893e3a59189f387f872ff07c2
2023-01-18Update for RESCALE spec apply_add clarificationJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I6958904c2c8932e9fe03b3092672d62a06e96ee6
2023-01-13Reference model update for control flow operators supportJerry Ge
Rationale for making this change: - In the original design, for control flow operators like WhileOp, child blocks couldn't read the tensor variables (global consts) in the root level block, this patch added the machanism for child blocks to access their parent level block's tensors. - This change also relies on another serialization change on adding another layer of abtraction called Region: - Serialization patch: [region] Add TosaSerializationRegion to serialization_lib - Updated the corresponding python version of the serialization code: TosaSerializerRegion to python version of serialization_lib - This change also relies on the TOSA MLIR Translator change: Add RegionBuilder to TOSA MLIR Translator - Added the WhileOp related test cases: While, LSTM, GRU, RNN - Other related fixes Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: I13ae33628ad07e41d248e88652ce1328654694ab
2022-12-20Add explicit template instantiations for abstract classesJared Smolens
- Added missing explicit template instantiations for abstract operator base classes Change-Id: I5eb678837f0edaf9bad0f7358b05abc5e3246af4 Signed-off-by: Jared Smolens <jared.smolens@arm.com>
2022-12-09Fix reference model memory leaks for the following opsJerry Ge
- OpClamp - OpArithmeticRightShift - OpMul - OpTable - OpTranspose Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: Icb84a8a17c298b471a635310454775977a9133cb
2022-11-29FP16 improvementsJames Ward
* Update FP16 resize to newest spec version * Correct casting to fp16 for graphs of >1 ops Change-Id: Iedff9a71eb7f72948b3c00a635bb0fd07d414bcd Signed-off-by: James Ward <james.ward@arm.com>
2022-11-19Fix the floating point precision issue for Sigmoid FP32Jerry Ge
The original calculation was auto-promoted to FP64 and causing the discrepencies between TFL and TOSA. Sigmoid is now calculated with only single precision floating point values. Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: Ia65b491ccf8af2493cc01ca66c28faff841407c2
2022-11-18Zero point addition in RESCALE should be int32Eric Kunze
Clipping to the output range is done post zero point addition. Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I5271a08fb2f6f9804fb1af3c6945131f948f452a
2022-11-09Add BF16 support to reference modelJames Ward
* Upgrade Eigen to 3.4.0 (for bfloat16 support) and add work- arounds for reduce.any() and reduce.all() bugs (introduced between 3.3.7 and 3.4.0) * Truncation to bfloat16 now performed in eval() methods Signed-off-by: James Ward <james.ward@arm.com> Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: If5f5c988d76d3d30790acf3b97081726b89205fe
2022-10-13Rename FLOAT type to FP32Jeremy Johnson
Update tensor operations naming to state input type as TxT in all cases. Effects CONV2D, CONV3D, DEPTHWISE_CONV2D, FULLY_CONNECTED, TRANSPOSE_CONV2D. Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ic959acfcb3aa0a910b33b774a5a85fac08219205
2022-10-11Reference model changes for fp16 supportJames Ward
Change-Id: I72f21fcfa153046274969d327313e3349981dbe6 Signed-off-by: James Ward <james.ward@arm.com>
2022-08-29Update framework test generator to support TF/TFL conv3d.TatWai Chong
Add a new attribute `rank` to indicate the testing dimension range of input tensor. Also fix a minor bug in the existing conv3d simulation. And relax rescale operator in the reference model to support 5-D input. Change-Id: Ib42fe513831dc83eb7f9af07e011787a6c752704 Signed-off-by: TatWai Chong <tatwai.chong@arm.com>
2022-08-26Align padding for transpose_conv2d to match specEric Kunze
Increasing out pad values now leads to increasing pad. Reference model changes, and test generator changes to match specification definition Change-Id: I4f3ebfbca5048354fb15bedc7ab640ff28ed853a Signed-off-by: Eric Kunze <eric.kunze@arm.com> Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com>
2022-08-24Enabled 16-bit TABLE REQUIRE statementJerry Ge
Signed-off-by: Jerry Ge <jerry.ge@arm.com> Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ib6e81814e022f33e45430e47ca99d6d9f9e0e101
2022-08-15Check that the shape calculation for PAD is correctEric Kunze
Matches a corresponding change to the specification Change-Id: If70356e0c78c1c88530e5d2f58bc50de864f249a Signed-off-by: Eric Kunze <eric.kunze@arm.com>
2022-08-10Update TOSA resize to match specificationTatWai Chong
Attribute stride and shift are removed, and has new scale and border. Also add tests in the generator to test tf.resize with all option combinations. Signed-off-by: TatWai Chong <tatwai.chong@arm.com> Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: If0f330d04395762d2d907863235eda1532f5e1ff
2022-06-17Fix reference model use of weight zero pointv0.30.0v0.30Eric Kunze
In the case of an int16xint8 test, the zero point was not being subtracted from the weights. Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: Ic77119b200b952715870abc11d09d1a646da86b1
2022-06-15Remove quantization info from serialization attributesEric Kunze
Any needed information moves into the attributes for each operator. New serialization library version removes teh quantization information attributes from the schema Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: Icf6165687ab1fd34a01f64c01b0b92b2820e72fa
2022-06-13Update transpose_conv2d to align with TOSA specTatWai Chong
Rename outpad to out_pad, and also fix the dilation in the generator. Change-Id: I4c1599871f0d0b41856e819d8c644a85ca6d8267 Signed-off-by: TatWai Chong <tatwai.chong@arm.com>
2022-06-07Remove dilation from transpose_conv2d opEric Kunze
It is not in the spec and is being removed from serialization Change-Id: I82a102de37d8eb75210088dfda2df9b2fadb9c74 Signed-off-by: Eric Kunze <eric.kunze@arm.com>
2022-06-07Change size check in TILE to ERROR_IFEric Kunze
Now corresponds with the ERROR_IF in the specification Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I1f4e303c330d18661ca2e6ef65d0119baabedec6
2022-06-07Align the serialization schema with TOSA 0.24.0 specificationTatWai Chong
The operators are pool, conv, reshape, slice, transpose, and table. Signed-off-by: TatWai Chong <tatwai.chong@arm.com> Change-Id: I13f8d626df59be14361068222746347ba69d2fb5
2022-05-31Remove RESHAPE -1 dimensions supportJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I098daf49c92da12c07143cdd23ac9bb58acebbb9
2022-05-26Add support for uint16_t to RESCALEJeremy Johnson
Update ref-model RESCALE op to support UINT16 conversions Add testing for RESCALE UINT16 and ERROR_IFs Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ic6e6e53de1f0b054bedb9e6ba3856e7475498aba
2022-05-16Initialize accumulator with bias value for CONV3DEric Kunze
Bias was mistakenly unused previously. Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: If776e923f7b3cd442c7f147fcbd22a214c37fd36
2022-05-16Adjust divisor calculationEric Kunze
Fixes issue where pad_left < stride would cause padding values to be missed Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I2ba0d0969ce1f00e2cb3ca1ab293c5e15a0c7749
2022-05-04Fix for NEGATE using 32-bit accumulatorJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ie5d119dc317303a0d2a71d018ac94ce6800ecbf5
2022-04-28Update tensor ops ERROR_IF criteriaJeremy Johnson
Update to ref model to check ERROR_IF criteria for pooling and convolution ops to match specification Update to tosa_verif_build_tests to produce valid test ranges and new ERROR_IF tests Plus update pooling ops big kernel to 9 (from 6) for better testing coverage and set dilation to 1 and add out_pad bottom & right for transpose_conv2d to match specification Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ic5759872d40ae8d3f3d07043d9a0f2fa0244d72e
2022-04-05Add missing REQUIREs check to REDUCE_SUM in refmodelJeremy Johnson
And limit REDUCE_SUM test values to within int32 Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I4d902b245d17eb343cfb2bbc23d9db28c1d1f4c3
2022-03-24Add missing REQUIRE to NEGATE opJeremy Johnson
And update test generation to create values in predictable range Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I4ba1ff445bf6caeec9f8782902fc45929fe0ee77
2022-03-10Fix refmodel LOGICAL_XOR (was incorrectly LOGICAL_OR)Jeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ifa34021413cd6543c987a7b7c9c664144a4dd95d
2022-02-01Rework divisor calculation for AVGPOOL2DEric Kunze
Previous code assumed symmetric padding when calculating the divisor for the average pool, and had issues with extra padding. The padding now follows the definition from the specification. Extra padding to the right/bottom is ignored when calculating the average pool divisor. Change-Id: Ib05e2346c6e9d55b6fef5294322e58ee18ef4928
2022-01-20Fix for LOGICAL_LEFT/RIGHT_SHIFT shift valuesJeremy Johnson
Added missing reference model REQUIRE check for shift value (0-31) Make sure result of LOGICAL_SHIFT_LEFT is masked to input size Fixed test generation to produce shift values in that range Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Id511de0d989ea954fc1afd18dc2051341bce2cd0
2021-11-11More ERROR_IF to check attribute for convolution opsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I49d498dd3d4c069d8d1db07310f939268b9df4b7
2021-11-09Check valid broadcastable shape for binary and ternary opsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I9ed3d8971a133b4cbb2cf7d827f4e69d55dee246
2021-11-02more ERROR_IF fixesKevin Cheng
- TRANSPOSE: move perm attribute check to compile-time checker - TABLE: add output type checker Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I834a5f290fbc384ef339b624060e6e5c77072c36
2021-11-01Fix for tensor_ops.ccKevin Cheng
- MATMUL: only check a_zp/b_zp valid when this->qinfo exists - Fix typo in debug message Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I2cedcb25e4f57fcaec2caa1b850ea1232a023340
2021-10-28Changes for 0.23.0 releaseKevin Cheng
- update serialization_lib hash - PAD: 1. make padding as an attribute instead of tensor. 2. add pad_const_int (for non-float type) / pad_const_fp (for float type) - TRANSPOSE: make perm as an attribute instead of tensor - TABLE: make table as attribute instead of tensor - update examples/ tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Iddc446db4b356ba2f36ea4a79b7220b9cfc2aa4e
2021-10-21Fix typo in Concat ERROR_IFKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I37fa4fedbeb64c1e147f2b43f45cf8e25854256c
2021-10-21Fix pool2d generation and check to match specificationJeremy Johnson
Change output size error_if check in ref model to match specification. Remove size check from test generation as output shape is always correctly calculated. Change-Id: I5be64f31e6448b47e80fc0a4af11bb312f366a26 Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com>
2021-10-18Add ERROR_IF to control flow ops.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ifd771171904d1e5a9db3ea1cae3ac9017e971c8c
2021-10-18More ERROR_IF supportsKevin Cheng
- Also delay tensor allocation after operator being validated ERROR_IF can be caught first before 0 or negative dimension set the graph_status to UNPREDICTABLE - Rescale, Argmax, FullyConnected, Matmul, Pad, Reshape, Slice, Transpose, Clamp, Concat, Equal, Greater, GreaterEqual, Table Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I4e1b3e5794fe195ce1a37e28443ae584645a3b91
2021-10-13Catch ERROR_IF on AVG_POOL2D and MAX_POOL2DKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I0947f136e768605f997fcaf74c6b9a7e62e748a4
2021-10-06Fix reduction ERROR_IF casesKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Id0e4ec849a9cf94c9fb04ca999738cc164dbb669
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