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2022-06-07Remove dilation from transpose_conv2d opEric Kunze
It is not in the spec and is being removed from serialization Change-Id: I82a102de37d8eb75210088dfda2df9b2fadb9c74 Signed-off-by: Eric Kunze <eric.kunze@arm.com>
2022-06-07Change size check in TILE to ERROR_IFEric Kunze
Now corresponds with the ERROR_IF in the specification Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I1f4e303c330d18661ca2e6ef65d0119baabedec6
2022-06-07Align the serialization schema with TOSA 0.24.0 specificationTatWai Chong
The operators are pool, conv, reshape, slice, transpose, and table. Signed-off-by: TatWai Chong <tatwai.chong@arm.com> Change-Id: I13f8d626df59be14361068222746347ba69d2fb5
2022-05-31Remove RESHAPE -1 dimensions supportJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I098daf49c92da12c07143cdd23ac9bb58acebbb9
2022-05-26Add support for uint16_t to RESCALEJeremy Johnson
Update ref-model RESCALE op to support UINT16 conversions Add testing for RESCALE UINT16 and ERROR_IFs Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ic6e6e53de1f0b054bedb9e6ba3856e7475498aba
2022-05-16Initialize accumulator with bias value for CONV3DEric Kunze
Bias was mistakenly unused previously. Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: If776e923f7b3cd442c7f147fcbd22a214c37fd36
2022-05-16Adjust divisor calculationEric Kunze
Fixes issue where pad_left < stride would cause padding values to be missed Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I2ba0d0969ce1f00e2cb3ca1ab293c5e15a0c7749
2022-05-04Fix for NEGATE using 32-bit accumulatorJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ie5d119dc317303a0d2a71d018ac94ce6800ecbf5
2022-04-28Update tensor ops ERROR_IF criteriaJeremy Johnson
Update to ref model to check ERROR_IF criteria for pooling and convolution ops to match specification Update to tosa_verif_build_tests to produce valid test ranges and new ERROR_IF tests Plus update pooling ops big kernel to 9 (from 6) for better testing coverage and set dilation to 1 and add out_pad bottom & right for transpose_conv2d to match specification Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ic5759872d40ae8d3f3d07043d9a0f2fa0244d72e
2022-04-05Add missing REQUIREs check to REDUCE_SUM in refmodelJeremy Johnson
And limit REDUCE_SUM test values to within int32 Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I4d902b245d17eb343cfb2bbc23d9db28c1d1f4c3
2022-03-24Add missing REQUIRE to NEGATE opJeremy Johnson
And update test generation to create values in predictable range Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I4ba1ff445bf6caeec9f8782902fc45929fe0ee77
2022-03-10Fix refmodel LOGICAL_XOR (was incorrectly LOGICAL_OR)Jeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ifa34021413cd6543c987a7b7c9c664144a4dd95d
2022-02-01Rework divisor calculation for AVGPOOL2DEric Kunze
Previous code assumed symmetric padding when calculating the divisor for the average pool, and had issues with extra padding. The padding now follows the definition from the specification. Extra padding to the right/bottom is ignored when calculating the average pool divisor. Change-Id: Ib05e2346c6e9d55b6fef5294322e58ee18ef4928
2022-01-20Fix for LOGICAL_LEFT/RIGHT_SHIFT shift valuesJeremy Johnson
Added missing reference model REQUIRE check for shift value (0-31) Make sure result of LOGICAL_SHIFT_LEFT is masked to input size Fixed test generation to produce shift values in that range Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Id511de0d989ea954fc1afd18dc2051341bce2cd0
2021-11-11More ERROR_IF to check attribute for convolution opsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I49d498dd3d4c069d8d1db07310f939268b9df4b7
2021-11-09Check valid broadcastable shape for binary and ternary opsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I9ed3d8971a133b4cbb2cf7d827f4e69d55dee246
2021-11-02more ERROR_IF fixesKevin Cheng
- TRANSPOSE: move perm attribute check to compile-time checker - TABLE: add output type checker Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I834a5f290fbc384ef339b624060e6e5c77072c36
2021-11-01Fix for tensor_ops.ccKevin Cheng
- MATMUL: only check a_zp/b_zp valid when this->qinfo exists - Fix typo in debug message Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I2cedcb25e4f57fcaec2caa1b850ea1232a023340
2021-10-28Changes for 0.23.0 releaseKevin Cheng
- update serialization_lib hash - PAD: 1. make padding as an attribute instead of tensor. 2. add pad_const_int (for non-float type) / pad_const_fp (for float type) - TRANSPOSE: make perm as an attribute instead of tensor - TABLE: make table as attribute instead of tensor - update examples/ tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Iddc446db4b356ba2f36ea4a79b7220b9cfc2aa4e
2021-10-21Fix typo in Concat ERROR_IFKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I37fa4fedbeb64c1e147f2b43f45cf8e25854256c
2021-10-21Fix pool2d generation and check to match specificationJeremy Johnson
Change output size error_if check in ref model to match specification. Remove size check from test generation as output shape is always correctly calculated. Change-Id: I5be64f31e6448b47e80fc0a4af11bb312f366a26 Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com>
2021-10-18Add ERROR_IF to control flow ops.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ifd771171904d1e5a9db3ea1cae3ac9017e971c8c
2021-10-18More ERROR_IF supportsKevin Cheng
- Also delay tensor allocation after operator being validated ERROR_IF can be caught first before 0 or negative dimension set the graph_status to UNPREDICTABLE - Rescale, Argmax, FullyConnected, Matmul, Pad, Reshape, Slice, Transpose, Clamp, Concat, Equal, Greater, GreaterEqual, Table Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I4e1b3e5794fe195ce1a37e28443ae584645a3b91
2021-10-13Catch ERROR_IF on AVG_POOL2D and MAX_POOL2DKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I0947f136e768605f997fcaf74c6b9a7e62e748a4
2021-10-06Fix reduction ERROR_IF casesKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Id0e4ec849a9cf94c9fb04ca999738cc164dbb669
2021-10-05Couple of reference model fixesKevin Cheng
- comparison ops could have different type of input/output - add SUBGRAPH_ERROR_IF() when operator doesn't have any output tensor Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I10f2c10f92de1c7a979221a421fa8e86b26fcc72
2021-09-30Fixes to pass NEGATE op test.Kevin Cheng
- Elementwise unary op input/output type should match. - TOSA_UNPREDICTABLE should ONLY be sent when a tensor with negative dimension is read/written Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I689518933a2b56cd62793e3f28ea66a6e57b057c
2021-09-30Add SUBGRAPH_ERROR_IF() to catch graph-level error.Kevin Cheng
- Also replace SIMPLE_FATAL_ERROR() with FATAL_ERROR() since they're duplicate - Replace FATAL_ERROR()/ASSERT_MSG() with ERROR_IF_SUBGRAPH() if the condition is a graph error FATAL_ERROR()/ASSERT() should only be used by model internal/runtime error like file reading. Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: If1e1e2488054a0ecd800fb0f2ea6487019282500
2021-09-28Remove ReluN op.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Iaac727159a84de1f83de549c3a22704096f46bf9
2021-09-28Removing rank 0 broadcast in binary op.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I14bec5020c91f7abd6c1adc31068a22961330a97
2021-09-23Add stride larger than dimension error_if check for resizeMatthew Haddon
Change-Id: Ib70f6bdbfacfe125283821f1e3858542b05c60ad Signed-off-by: Matthew Haddon <matthew.haddon@arm.com>
2021-09-20Add maximum dimension check ERROR_IF in RESIZE.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Iccbabe4298de4bd681115e273c16c48ea6d3028e
2021-09-16Implement Conv3D kernel.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ic16e918b1a2423ad563684e29ce70d9efdbf9c02
2021-09-15Rename attribute: Pool2d, Conv2d, TransposeConv2d -> Pool, Conv, TransposeConvKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I466dd1dcf5230e8e07df202ba88515e775e04a1e
2021-09-14Add saturation REQUIREs for ADD,SUB,MUL,INTDIVJeremy Johnson
Change-Id: I358fbd4c958e057687f25d585eb8fdd80fd9ae42 Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com>
2021-08-31Rename DIV operator to INTDIVMatthew Haddon
* In line with the TOSA spec the DIV operator has been renamed INTDIV Signed-off-by: Matthew Haddon <matthew.haddon@arm.com> Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I1dc6e88220ef26b24487675600b6cd1e5bb8b0f7
2021-08-20Replace node level check ASSERT_MSG_NODE()/FATAL_ERROR_NODE() with REQUIRE() ↵Kevin Cheng
or ERROR_IF() - Adding return code enum class: {VALID, UNPREDICTABLE, ERROR} - Runtime errors (e.g. memory allocation failure) will abort immediately, or will return one of the three return codes Part of the codes are re-written to pass REQUIRE() to the top-level (e.g. apply_scale_32/16()) - Update setExpectedFailure() to setExpectedReturnCode() on test generation script - Update test regression script to interface with reference model change Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ia063c936bcb2a54d6e379a5bb6801aa72d1186f1
2021-06-09adding batch dimension to MatMul.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I83f75dd5beb60fe7ca2d573ea0f81bac4cd62a07
2021-05-24Support 8-bit TABLE op.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: If577035d71c5f9970df5b6a78640a3028c3f83c0
2021-05-12Update to v0.22.0Kevin Cheng
- remove identityN and placeholder - add div - update serialization_lib hash - update apply_scale_16() assertion - regenerate examples/ due to serialization_lib change Change-Id: I7183d92bec33697c65adfc07cb8eb89c6882675a
2021-04-30Fix OpMul for 32-bit x 32-bit inputsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I068d3ce0bffe1b49845f0c8cd39130060cceaf19
2021-04-30Support 16-bit RescaleKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ifc80b83c1abcd08e1b7f8e50f647b74c861bc933
2021-04-30Concat takes variadic inputsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ic8fe6e1fd899b41d444fd4f477d0f515ce0e9cc9
2021-04-27Replace serialization/ and verif/ with MLPlatform's serialization_lib submoduleKevin Cheng
- Remove Usage and Format - Run black on verif/*.py scripts Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ie81515891eb0039540f614894f4b6b0e0e78ba74
2021-04-23Fix bug that NegateOp doesn't clip output valueKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I6b335605d79338fc77e3f84585aeffe1e61cb1f2
2021-02-01Remove AINT8Kevin Cheng
- Updated C and Py serialization libraries, updated licence files - Removed AINT8 from TOSA reference tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Signed-off-by: Jared Smolens <jared.smolens@arm.com> Change-Id: I860bfeaad5a075e50f569c8f6861927ebacf1378
2020-11-24Update reference model/serialization library to 0.21.0 with unit tests ↵Kevin Cheng
added/updated - update tosa.GATHER - update tosa.RESIZE - add tosa.SCATTER Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I1c3247b831a64e35a85c4044b24c6c29b8e18d25
2020-11-12Implement and add unit tests for MUL and ARITHMETIC_RIGHT_SHIFTKevin Cheng
add .clang-format Add expected failure for RESIZE and RESCALE unit tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I33c8afdc8998e8518f2b0e5fabddd36ce3aa2ee9
2020-10-19Update apply_scale_32()Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ida8e3a17d74e5d6379b2244896ddf9e295d0ecc9
2020-10-14Initial checkin of TOSA reference_model and testsEric Kunze
Change-Id: I2f8e7fa63e2ae40203e57d2cc8814bde3b312cb6 Signed-off-by: Eric Kunze <eric.kunze@arm.com>
generated by cgit v1.2.1 (git 2.23.0) at 2024-06-11 18:52:34 +0000