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9 daysChange the table parameter from attribute to tensor typeTatWai Chong
also add testing support for table parameter as input. Signed-off-by: TatWai Chong <tatwai.chong@arm.com> Change-Id: Ie4f6d3cf0b68803fa3353cfa0e9f7f38a83b1539
2024-05-01Fix MAXIMUM/MINIMUM handling of NaNs and zeroesJeremy Johnson
Change FP_SPECIAL testing to be used for DOT_PRODUCT cases only. Use default EXACT matching - where zeroes of different signs will be ignored when testing for equality Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I0461c42258611cae597f693507075b3ef15fbe19
2024-03-01Testing support for MUL with shift as inputJeremy Johnson
Always create the shift as a tensor for all types in testing. In the reference model, set the shift operand to be available for all types, but only read in the shift tensor for i32. Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Signed-off-by: TatWai Chong <tatwai.chong@arm.com> Change-Id: Ia267cbf8b63ca0a9c97b38e8fb4db83eeb8c0538
2024-02-22Change the shift of mul to tensor typeTatWai Chong
Right shift result on i32_t data type only, i.e. other data types don't carry the shift operand. In the spec, the shift type is a tensor in MT profile and is an attribute in BI/MI profiles. Currently we treat the shift as tensor throughout. In implementation, since `ternaryExpr` is not implemented in Eigen, decompose the original calculation into multiply and shift operation seperately, and execute them via `binaryExpr`. Change-Id: I349f4969545134ac5f13bc83032cd75cca3e7ba0 Signed-off-by: TatWai Chong <tatwai.chong@arm.com>
2024-02-07Main Compliance: Update POW error boundJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I8f7678706e517d7f8d9742dcddd0ea5875b30a00
2024-01-25Fix logical right shift operator for signed negative integersWon Jeon
Signed-off-by: Won Jeon <won.jeon@arm.com> Change-Id: Id37100ba8bc2ac64b1f54788c6f765fedfab0816
2023-12-05Fix Format Specifiers for MUL REQUIRES outputJack Frankland
Use platform agnostic format specifiers for `int64_t`. Change-Id: I002d94c1a0c0431ec09fc165a584a8f4b3ddc17d Signed-off-by: Jack Frankland <jack.frankland@arm.com>
2023-11-16Main Compliance testing support for EXP & POWJeremy Johnson
Added new ABS_ERROR mode to verify lib and ref model. Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ifb78290675833d3df7df91a4d6cef336b02b64a4
2023-08-02Fix compiler warnings (NFC)Eric Kunze
Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I8645382983c257e5102982d487283560088e2d2a
2023-07-25Run clang-format and update copyrightJerry Ge
- Also added run clang-format to pre-commit runs Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: I4e59ac0afbaa30dce0773aa63d92a1a3b119e2f3
2023-06-29Fix missing template instantiationsEric Kunze
Would cause unresolved symbols to appear when building in release mode. There are a couple of minor compiler warning fixes as well. Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: I0f7e9a8771442a6e3c848edfe034ef534d0d8ca7
2023-06-15Add ERROR_IF to incorrect broadcast shapesJerry Ge
Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: I7460ad9eed3ed5c7cec6e855a0303753ed28eb1c
2023-05-10Refactor ref_model rank checking and add level check to argmaxJerry Ge
Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: Iad035b31d5e5e83040068e6311501490765bfff7
2023-05-05[reference model] Add precise modeTai Ly
This adds --precise_mode=1 option to tosa_referece_model, which will cause reference model to convert all floating point tensors to FP64 tensors and compute all operators accordingly. Also adds optional -p arguments to test runners tosa_verif_run_tests.py and tosa_verif_framework_compiler_runner.py to run tests in precise mode Signed-off-by: Tai Ly <tai.ly@arm.com> Change-Id: I156055216ad61710096497a8fa1a653be2a602a3
2023-04-20Add level checking to TOSA Ref modelJerry Ge
Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: I5689d7c6b902a319a68fa4628b59e0bcc23aeca4
2023-03-17Refactor 1L to INT64_C()Jerry Ge
Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: If3f8c5a1f2dffac36448101959557f86b6ab6c7f
2023-01-19Fix for sign extending LOGICAL LEFT/RIGHT SHIFT resultsJeremy Johnson
Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: I04261178694c004409aef2ff5c84c32b04729433
2022-12-20Add explicit template instantiations for abstract classesJared Smolens
- Added missing explicit template instantiations for abstract operator base classes Change-Id: I5eb678837f0edaf9bad0f7358b05abc5e3246af4 Signed-off-by: Jared Smolens <jared.smolens@arm.com>
2022-12-09Fix reference model memory leaks for the following opsJerry Ge
- OpClamp - OpArithmeticRightShift - OpMul - OpTable - OpTranspose Signed-off-by: Jerry Ge <jerry.ge@arm.com> Change-Id: Icb84a8a17c298b471a635310454775977a9133cb
2022-11-09Add BF16 support to reference modelJames Ward
* Upgrade Eigen to 3.4.0 (for bfloat16 support) and add work- arounds for reduce.any() and reduce.all() bugs (introduced between 3.3.7 and 3.4.0) * Truncation to bfloat16 now performed in eval() methods Signed-off-by: James Ward <james.ward@arm.com> Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: If5f5c988d76d3d30790acf3b97081726b89205fe
2022-10-13Rename FLOAT type to FP32Jeremy Johnson
Update tensor operations naming to state input type as TxT in all cases. Effects CONV2D, CONV3D, DEPTHWISE_CONV2D, FULLY_CONNECTED, TRANSPOSE_CONV2D. Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ic959acfcb3aa0a910b33b774a5a85fac08219205
2022-10-11Reference model changes for fp16 supportJames Ward
Change-Id: I72f21fcfa153046274969d327313e3349981dbe6 Signed-off-by: James Ward <james.ward@arm.com>
2022-08-24Enabled 16-bit TABLE REQUIRE statementJerry Ge
Signed-off-by: Jerry Ge <jerry.ge@arm.com> Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Ib6e81814e022f33e45430e47ca99d6d9f9e0e101
2022-06-15Remove quantization info from serialization attributesEric Kunze
Any needed information moves into the attributes for each operator. New serialization library version removes teh quantization information attributes from the schema Signed-off-by: Eric Kunze <eric.kunze@arm.com> Change-Id: Icf6165687ab1fd34a01f64c01b0b92b2820e72fa
2022-01-20Fix for LOGICAL_LEFT/RIGHT_SHIFT shift valuesJeremy Johnson
Added missing reference model REQUIRE check for shift value (0-31) Make sure result of LOGICAL_SHIFT_LEFT is masked to input size Fixed test generation to produce shift values in that range Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com> Change-Id: Id511de0d989ea954fc1afd18dc2051341bce2cd0
2021-11-09Check valid broadcastable shape for binary and ternary opsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I9ed3d8971a133b4cbb2cf7d827f4e69d55dee246
2021-11-02more ERROR_IF fixesKevin Cheng
- TRANSPOSE: move perm attribute check to compile-time checker - TABLE: add output type checker Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I834a5f290fbc384ef339b624060e6e5c77072c36
2021-10-28Changes for 0.23.0 releaseKevin Cheng
- update serialization_lib hash - PAD: 1. make padding as an attribute instead of tensor. 2. add pad_const_int (for non-float type) / pad_const_fp (for float type) - TRANSPOSE: make perm as an attribute instead of tensor - TABLE: make table as attribute instead of tensor - update examples/ tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Iddc446db4b356ba2f36ea4a79b7220b9cfc2aa4e
2021-10-18More ERROR_IF supportsKevin Cheng
- Also delay tensor allocation after operator being validated ERROR_IF can be caught first before 0 or negative dimension set the graph_status to UNPREDICTABLE - Rescale, Argmax, FullyConnected, Matmul, Pad, Reshape, Slice, Transpose, Clamp, Concat, Equal, Greater, GreaterEqual, Table Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I4e1b3e5794fe195ce1a37e28443ae584645a3b91
2021-10-05Couple of reference model fixesKevin Cheng
- comparison ops could have different type of input/output - add SUBGRAPH_ERROR_IF() when operator doesn't have any output tensor Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I10f2c10f92de1c7a979221a421fa8e86b26fcc72
2021-09-28Removing rank 0 broadcast in binary op.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I14bec5020c91f7abd6c1adc31068a22961330a97
2021-09-14Add saturation REQUIREs for ADD,SUB,MUL,INTDIVJeremy Johnson
Change-Id: I358fbd4c958e057687f25d585eb8fdd80fd9ae42 Signed-off-by: Jeremy Johnson <jeremy.johnson@arm.com>
2021-08-31Rename DIV operator to INTDIVMatthew Haddon
* In line with the TOSA spec the DIV operator has been renamed INTDIV Signed-off-by: Matthew Haddon <matthew.haddon@arm.com> Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I1dc6e88220ef26b24487675600b6cd1e5bb8b0f7
2021-08-20Replace node level check ASSERT_MSG_NODE()/FATAL_ERROR_NODE() with REQUIRE() ↵Kevin Cheng
or ERROR_IF() - Adding return code enum class: {VALID, UNPREDICTABLE, ERROR} - Runtime errors (e.g. memory allocation failure) will abort immediately, or will return one of the three return codes Part of the codes are re-written to pass REQUIRE() to the top-level (e.g. apply_scale_32/16()) - Update setExpectedFailure() to setExpectedReturnCode() on test generation script - Update test regression script to interface with reference model change Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: Ia063c936bcb2a54d6e379a5bb6801aa72d1186f1
2021-05-24Support 8-bit TABLE op.Kevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: If577035d71c5f9970df5b6a78640a3028c3f83c0
2021-05-12Update to v0.22.0Kevin Cheng
- remove identityN and placeholder - add div - update serialization_lib hash - update apply_scale_16() assertion - regenerate examples/ due to serialization_lib change Change-Id: I7183d92bec33697c65adfc07cb8eb89c6882675a
2021-04-30Fix OpMul for 32-bit x 32-bit inputsKevin Cheng
Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I068d3ce0bffe1b49845f0c8cd39130060cceaf19
2021-02-01Remove AINT8Kevin Cheng
- Updated C and Py serialization libraries, updated licence files - Removed AINT8 from TOSA reference tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Signed-off-by: Jared Smolens <jared.smolens@arm.com> Change-Id: I860bfeaad5a075e50f569c8f6861927ebacf1378
2020-11-12Implement and add unit tests for MUL and ARITHMETIC_RIGHT_SHIFTKevin Cheng
add .clang-format Add expected failure for RESIZE and RESCALE unit tests Signed-off-by: Kevin Cheng <kevin.cheng@arm.com> Change-Id: I33c8afdc8998e8518f2b0e5fabddd36ce3aa2ee9
2020-10-14Initial checkin of TOSA reference_model and testsEric Kunze
Change-Id: I2f8e7fa63e2ae40203e57d2cc8814bde3b312cb6 Signed-off-by: Eric Kunze <eric.kunze@arm.com>
generated by cgit v1.2.1 (git 2.23.0) at 2024-06-06 11:24:22 +0000