Reference model update for control flow operators support

Rationale for making this change:
- In the original design, for control flow operators like WhileOp,
child blocks couldn't read the tensor variables (global consts) in the root level block,
this patch added the machanism for child blocks to access their parent
level block's tensors.
- This change also relies on another serialization change on adding
another layer of abtraction called Region:
  - Serialization patch: [region] Add TosaSerializationRegion to serialization_lib
  - Updated the corresponding python version of the serialization code: TosaSerializerRegion to python version of serialization_lib
- This change also relies on the TOSA MLIR Translator change: Add RegionBuilder to TOSA MLIR Translator
- Added the WhileOp related test cases: While, LSTM, GRU, RNN
- Other related fixes

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
Change-Id: I13ae33628ad07e41d248e88652ce1328654694ab

1 files changed, 8 insertions, 1 deletions

diff --git a/reference_model/src/tensor.h b/reference_model/src/tensor.h
index 08e865a..d5f1de8 100644
--- a/reference_model/src/tensor.h
+++ b/reference_model/src/tensor.h
@@ -1,5 +1,5 @@
 
-// Copyright (c) 2020-2022, ARM Limited.
+// Copyright (c) 2020-2023, ARM Limited.
 //
 //    Licensed under the Apache License, Version 2.0 (the "License");
 //    you may not use this file except in compliance with the License.
@@ -40,6 +40,11 @@ public:
 
     int setIsSubgraphInput();
     int setIsSubgraphOutput();
+    int setIsParentGraphOutput();
+
+    int getIsParentGraphOutput() const {
+        return isParentGraphOutput;
+    }
 
     int getIsSubgraphInput() const
     {
@@ -261,6 +266,8 @@ protected:
     int isSubgraphOutput;
     bool isAllocated;
 
+    bool isParentGraphOutput;
+
     GraphNode* producer;
     std::vector<GraphNode*> consumers;