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| author | Kevin Cheng <kevin.cheng@arm.com> | 2021-05-13 17:41:28 -0700 |
|---|---|---|
| committer | Kevin Cheng <kevin.cheng@arm.com> | 2021-05-13 17:41:28 -0700 |
| commit | 47315e1af6947dd93729c6dbd034c7db1af7f312 (patch) | |
| tree | 9ec52894ab993a225a95838d0501db8fefcfb420 | |
| parent | 14d7f7a2b5d0d85b83d8c84a5456828feb1a0ea1 (diff) | |
| download | reference_model-47315e1af6947dd93729c6dbd034c7db1af7f312.tar.gz | |
Fix typo in DIV unit test generator
Change-Id: Id253b62af906a7ffbdbc0d338b6ec92d3795d1c6
| -rw-r--r-- | verif/tosa_test_gen.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/verif/tosa_test_gen.py b/verif/tosa_test_gen.py index bc97f15..5670d1b 100644 --- a/verif/tosa_test_gen.py +++ b/verif/tosa_test_gen.py @@ -1723,7 +1723,7 @@ class TosaTestGen: # Two invalid cases for Op.DIV: # 1. divisor == 0 - # 2. dividend == (1<<31) and divisor == -1 + # 2. dividend == -(1<<31) and divisor == -1 while True: dividend_arr = self.getRandTensor(shapeList[0], dtypeList[0]) divisor_arr = self.getRandTensor(shapeList[1], dtypeList[1]) @@ -1731,7 +1731,7 @@ class TosaTestGen: if (divisor_arr == 0).any(): continue - if (dividend_arr == (2 ** 31)).any() and (divisor_arr == -1).any(): + if (dividend_arr == -(2 ** 31)).any() and (divisor_arr == -1).any(): continue break |