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| author | James Ward <james.ward@arm.com> | 2023-02-07 20:10:48 +0000 |
|---|---|---|
| committer | James Ward <james.ward@arm.com> | 2023-02-20 11:12:45 +0000 |
| commit | dca402e71ab73c9e5843eb5a1cba4c380f8874a9 (patch) | |
| tree | 4085e4c3262be4bbfa371702d50956599d663541 /operators/tensor/depthwise_conv2d_1x1/depthwise_conv2d_1x1_1x37x11x5_f32xf32_accf32_st12_pad1100_dilat12/test.json | |
| parent | 2e5ae1b56c08821a5e0dd7dac40d0a6d73acbadc (diff) | |
| download | conformance_tests-dca402e71ab73c9e5843eb5a1cba4c380f8874a9.tar.gz | |
Create MI tests for Tensors: DEPTHWISE_CONV2D
Signed-off-by: James Ward <james.ward@arm.com>
Change-Id: I1f414a68c4f532b3315ec5ffab932dd3d70407b5
Diffstat (limited to 'operators/tensor/depthwise_conv2d_1x1/depthwise_conv2d_1x1_1x37x11x5_f32xf32_accf32_st12_pad1100_dilat12/test.json')
| -rw-r--r-- | operators/tensor/depthwise_conv2d_1x1/depthwise_conv2d_1x1_1x37x11x5_f32xf32_accf32_st12_pad1100_dilat12/test.json | 199 |
1 files changed, 199 insertions, 0 deletions
diff --git a/operators/tensor/depthwise_conv2d_1x1/depthwise_conv2d_1x1_1x37x11x5_f32xf32_accf32_st12_pad1100_dilat12/test.json b/operators/tensor/depthwise_conv2d_1x1/depthwise_conv2d_1x1_1x37x11x5_f32xf32_accf32_st12_pad1100_dilat12/test.json new file mode 100644 index 000000000..36de50920 --- /dev/null +++ b/operators/tensor/depthwise_conv2d_1x1/depthwise_conv2d_1x1_1x37x11x5_f32xf32_accf32_st12_pad1100_dilat12/test.json @@ -0,0 +1,199 @@ +{ + version: { + _major: 0, + _minor: 51, + _patch: 0, + _draft: true + }, + regions: [ + { + name: "main", + blocks: [ + { + name: "main", + operators: [ + { + op: "CONST", + attribute_type: "NONE", + inputs: [ + + ], + outputs: [ + "const-1" + ] + }, + { + op: "CONST", + attribute_type: "NONE", + inputs: [ + + ], + outputs: [ + "const-2" + ] + }, + { + op: "DEPTHWISE_CONV2D", + attribute_type: "ConvAttribute", + attribute: { + pad: [ + 1, + 1, + 0, + 0 + ], + stride: [ + 1, + 2 + ], + dilation: [ + 1, + 2 + ], + input_zp: 0, + weight_zp: 0 + }, + inputs: [ + "input-0", + "const-1", + "const-2" + ], + outputs: [ + "result-0" + ] + } + ], + tensors: [ + { + name: "input-0", + shape: [ + 1, + 37, + 11, + 5 + ], + type: "FP32" + }, + { + name: "const-1", + shape: [ + 1, + 1, + 5, + 2 + ], + type: "FP32", + data: [ + 183, + 211, + 200, + 191, + 72, + 213, + 223, + 63, + 246, + 28, + 244, + 190, + 141, + 116, + 66, + 190, + 80, + 83, + 225, + 62, + 38, + 253, + 138, + 62, + 40, + 179, + 63, + 191, + 80, + 109, + 247, + 191, + 253, + 185, + 100, + 191, + 168, + 55, + 111, + 63 + ] + }, + { + name: "const-2", + shape: [ + 10 + ], + type: "FP32", + data: [ + 242, + 11, + 241, + 191, + 49, + 49, + 131, + 63, + 236, + 24, + 148, + 63, + 135, + 244, + 86, + 63, + 246, + 8, + 139, + 63, + 236, + 117, + 196, + 63, + 151, + 149, + 29, + 63, + 108, + 111, + 240, + 63, + 87, + 65, + 79, + 191, + 156, + 99, + 216, + 61 + ] + }, + { + name: "result-0", + shape: [ + 1, + 39, + 6, + 10 + ], + type: "FP32" + } + ], + inputs: [ + "input-0" + ], + outputs: [ + "result-0" + ] + } + ] + } + ] +} |