MLIA-551 Rework remains of AIET architecture

Re-factoring the code base to further merge the old AIET code into MLIA.

- Remove last traces of the backend type 'tool'
- Controlled systems removed, including SSH protocol, controller,
  RunningCommand, locks etc.
- Build command / build dir and deploy functionality removed from
  Applications and Systems
- Moving working_dir()
- Replace module 'output_parser' with new module 'output_consumer' and
  merge Base64 parsing into it
- Change the output consumption to optionally remove (i.e. actually
  consume) lines
- Use Base64 parsing in GenericInferenceOutputParser, replacing the
  regex-based parsing and remove the now unused regex parsing
- Remove AIET reporting
- Pre-install applications by moving them to src/mlia/resources/backends
- Rename aiet-config.json to backend-config.json
- Move tests from tests/mlia/ to tests/
- Adapt unit tests to code changes
- Dependencies removed: paramiko, filelock, psutil
- Fix bug in corstone.py: The wrong resource directory was used which
  broke the functionality to download backends.
- Use f-string formatting.
- Use logging instead of print.

Change-Id: I768bc3bb6b2eda57d219ad01be4a8e0a74167d76

1 files changed, 0 insertions, 47 deletions

diff --git a/tests/mlia/test_resources/vela/sample_vela.ini b/tests/mlia/test_resources/vela/sample_vela.ini
deleted file mode 100644
index c992458..0000000
--- a/tests/mlia/test_resources/vela/sample_vela.ini
+++ /dev/null
@@ -1,47 +0,0 @@
-; SPDX-FileCopyrightText: Copyright 2022, Arm Limited and/or its affiliates.
-; SPDX-License-Identifier: Apache-2.0
-; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s)
-[System_Config.Ethos_U55_High_End_Embedded]
-core_clock=500e6
-axi0_port=Sram
-axi1_port=OffChipFlash
-Sram_clock_scale=1.0
-Sram_burst_length=32
-Sram_read_latency=32
-Sram_write_latency=32
-OffChipFlash_clock_scale=0.125
-OffChipFlash_burst_length=128
-OffChipFlash_read_latency=64
-OffChipFlash_write_latency=64
-
-; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s)
-[System_Config.Ethos_U65_High_End]
-core_clock=1e9
-axi0_port=Sram
-axi1_port=Dram
-Sram_clock_scale=1.0
-Sram_burst_length=32
-Sram_read_latency=32
-Sram_write_latency=32
-Dram_clock_scale=0.234375
-Dram_burst_length=128
-Dram_read_latency=500
-Dram_write_latency=250
-
-; -----------------------------------------------------------------------------
-; Memory Mode
-
-; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software
-; The non-SRAM memory is assumed to be read-only
-[Memory_Mode.Shared_Sram]
-const_mem_area=Axi1
-arena_mem_area=Axi0
-cache_mem_area=Axi0
-
-; The SRAM (384KB) is only for use by the Ethos-U
-; The non-SRAM memory is assumed to be read-writeable
-[Memory_Mode.Dedicated_Sram]
-const_mem_area=Axi1
-arena_mem_area=Axi1
-cache_mem_area=Axi0
-arena_cache_size=393216