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; Copyright (c) 2021 Arm Limited. All rights reserved.
; SPDX-License-Identifier: Apache-2.0
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
;
; Sections used:
;---------------------------------------------------------
; | Start | End | Size | Remarks |
;-|-------------|-------------|-------------|------------|
; | 0x0000_0000 | 0x0010_0000 | 0x0010_0000 | ITCM (RO) |
; | 0x0010_0000 | 0x0030_0000 | 0x0020_0000 | BRAM (RW) |
; | 0x2000_0000 | 0x2040_0000 | 0x0040_0000 | DTCM (RW) |
; | 0x6000_0000 | 0x6200_0000 | 0x0200_0000 | DRAM (RW) |
;-|-------------|-------------|-------------|------------|
; ITCM is aliased at 0x1000_0000 (single bank)
; BRAM is aliased at 0x1010_0000
; DTCM is aliased at 0x3000_0000 (four banks of 1MiB each)
; DRAM is aliased at 0x7000_0000 (section is 256MiB)
;
; Note: Ethos-U55 can only access DRAM and BRAM sections
;---------------------------------------------------------
; First load region
;---------------------------------------------------------
LOAD_REGION_0 0x00000000 0x00100000
{
;-----------------------------------------------------
; First part of code mem - 1MiB
;-----------------------------------------------------
itcm.bin 0x00000000 0x00100000
{
*.o (RESET, +First)
* (InRoot$$Sections)
.ANY (+RO)
}
;-----------------------------------------------------
; Code memory's 2MiB - reserved for activation buffers
; Make sure this is uninitialised.
;-----------------------------------------------------
bram.bin 0x00100000 UNINIT 0x00200000
{
; activation buffers a.k.a tensor arena
*.o (.bss.NoInit.activation_buf)
}
;-----------------------------------------------------
; 1MiB bank is used for any other RW or ZI data
; Note: this region is internal to the Cortex-M CPU
;-----------------------------------------------------
dtcm.bin 0x20000000 0x00100000
{
.ANY(+RW +ZI)
}
;-----------------------------------------------------
; 128kiB of stack space within SRAM region
;-----------------------------------------------------
ARM_LIB_STACK 0x20100000 EMPTY ALIGN 8 0x00020000
{}
;-----------------------------------------------------
; 2MiB of heap space within the SRAM region
;-----------------------------------------------------
ARM_LIB_HEAP 0x20200000 EMPTY ALIGN 8 0x00200000
{}
}
;---------------------------------------------------------
; Second load region
;---------------------------------------------------------
LOAD_REGION_1 0x60000000 0x02000000
{
;-----------------------------------------------------
; 32 MiB of DRAM space for nn model and input vectors
;-----------------------------------------------------
dram.bin 0x60000000 0x02000000
{
; nn model's baked in input matrices
*.o (ifm)
; nn model
*.o (nn_model)
; if the activation buffer (tensor arena) doesn't
; fit in the SRAM region, we accommodate it here
*.o (activation_buf)
}
}
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