From f5907730c3cea2f1e2055a01d9f9afc7de0a6283 Mon Sep 17 00:00:00 2001 From: Isabella Gottardi Date: Fri, 6 Aug 2021 15:39:41 +0100 Subject: Fix documentation. * Fix broken link "building-for-different-ethos_u-npu-variants" * Corstone-300 + Ethos-U65 NPU support in memory_considerations Signed-off-by: Isabella Gottardi Change-Id: I2e99e2d24d3cd0bb64e06481862660d1b0679f20 --- .../hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct | 4 ++-- .../hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'source/application/hal/platforms/bare-metal') diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct index 55ed5d7..dd53a57 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct @@ -18,7 +18,7 @@ ; ************************************************************* ; Please see docs/sections/appendix.md for memory mapping information. ; -; Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and ; the model should only be placed in those regions. ; ;--------------------------------------------------------- @@ -63,7 +63,7 @@ LOAD_REGION_0 0x00000000 0x00080000 ; SSE-300's internal SRAM of 4MiB - reserved for ; activation buffers. ; This region should have 3 cycle read latency from - ; both Cortex-M55 and Ethos-U55 + ; both Cortex-M55 and Ethos-U NPU ;----------------------------------------------------- isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000 { diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct index deb4214..0c6a388 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct @@ -59,7 +59,7 @@ LOAD_REGION_0 0x00000000 0x00080000 ; SSE-300's internal SRAM of 4MiB - reserved for ; activation buffers. ; This region should have 3 cycle read latency from - ; both Cortex-M55 and Ethos-U55 + ; both Cortex-M55 and Ethos-U NPU ;----------------------------------------------------- isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000 { -- cgit v1.2.1