From 3c79893217bc632c9b0efa815091bef3c779490c Mon Sep 17 00:00:00 2001
From: alexander <alexander.efremov@arm.com>
Date: Fri, 26 Mar 2021 21:42:19 +0000
Subject: Opensource ML embedded evaluation kit

Change-Id: I12e807f19f5cacad7cef82572b6dd48252fd61fd
---
 .../bare-metal/bsp/cmsis-device/include/cmsis.h    | 31 +++++++++++++
 .../bare-metal/bsp/cmsis-device/include/irqs.h     | 54 ++++++++++++++++++++++
 2 files changed, 85 insertions(+)
 create mode 100644 source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/cmsis.h
 create mode 100644 source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/irqs.h

(limited to 'source/application/hal/platforms/bare-metal/bsp/cmsis-device/include')

diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/cmsis.h b/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/cmsis.h
new file mode 100644
index 0000000..969db15
--- /dev/null
+++ b/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/cmsis.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef BAREMETAL_CMSIS_H
+#define BAREMETAL_CMSIS_H
+
+#include "ARMCM55.h"  /* Cortex M system header file from CMSIS. */
+#include "irqs.h"     /* Interrupt definitions file. */
+
+/* Addition to template functions should be mentioned here. */
+
+/**
+ * @brief   Gets the internal processor clock.
+ * @return  Clock frequency as unsigned 32 bit value.
+ **/
+uint32_t GetSystemCoreClock(void);
+
+#endif  /* BAREMETAL_CMSIS_H */
diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/irqs.h b/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/irqs.h
new file mode 100644
index 0000000..0d8dec6
--- /dev/null
+++ b/source/application/hal/platforms/bare-metal/bsp/cmsis-device/include/irqs.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef IRQS_H
+#define IRQS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "peripheral_irqs.h"
+
+#include <stdint.h>
+
+/* Interrupt handler function type. */
+typedef void (*const irq_vec_type)(void);
+
+/**
+ *  @brief  Reset interrupt handler and also, the starting
+ *          point of the application.
+ **/
+extern void Reset_Handler(void);
+
+/**
+ * @brief   Gets the system tick triggered cycle counter for the CPU.
+ * @return  64-bit counter value.
+ **/
+extern uint64_t Get_SysTick_Cycle_Count(void);
+
+/**
+ * @brief   Initialises the system tick registers.
+ * @return  Error code return from sys tick configuration function
+ *          (0 = no error).
+ **/
+extern int Init_SysTick(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* IRQS_H */
-- 
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