From da2ec067da418d3d80b2829b111df25bd901eb5c Mon Sep 17 00:00:00 2001 From: Kshitij Sisodia Date: Fri, 1 Apr 2022 14:43:53 +0100 Subject: MLECO-3096: Removing "timer" from HAL profile. Attempting to have timer functionality contained within the platform drivers "package" as it should (in line with the refactoring work done so far under HAL). This will ensure that we don't need two timer implementations under HAL "profiles" and therefore, this whole directory can be removed. This change also addressed issue with the applicatio level Profiler code knowing about how the PMU has been set up by the platform code. This link has been removed completely. This will make it much easier to add/amend the Ethos-U PMU event counters types and give each platform the capability of populating their relvant counters. The application level Profiler doesn't know which metrics it is displaying but just calculates and maintains statistics for whatever PMU counters it receives from the HAL level. A fix for timing adapter issue introduced in the last CR is also included. Change-Id: Ia46e03a06e7b8e42b9ed2ba8f2af2dcd2229c110 Signed-off-by: Kshitij Sisodia --- docs/sections/building.md | 2 +- docs/sections/testing_benchmarking.md | 6 +----- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'docs') diff --git a/docs/sections/building.md b/docs/sections/building.md index 699667b..5f8a3cb 100644 --- a/docs/sections/building.md +++ b/docs/sections/building.md @@ -206,7 +206,7 @@ The build parameters are: `ETHOS_U_NPU_ID` is `U65`. Default value is 393216 (see [default_vela.ini](../../scripts/vela/default_vela.ini) ). - `CPU_PROFILE_ENABLED`: Sets whether profiling information for the CPU core should be displayed. By default, this is - set to false, but can be turned on for FPGA targets. The the FVP and the CPU core cycle counts are not meaningful and + set to false, but can be turned on for FPGA targets. The FVP and the CPU core cycle counts are **not** meaningful and are not to be used. - `LOG_LEVEL`: Sets the verbosity level for the output of the application over `UART`, or `stdout`. Valid values are: diff --git a/docs/sections/testing_benchmarking.md b/docs/sections/testing_benchmarking.md index d1cd9df..2641049 100644 --- a/docs/sections/testing_benchmarking.md +++ b/docs/sections/testing_benchmarking.md @@ -101,11 +101,7 @@ INFO - NPU TOTAL cycles: 1081634 INFO - Profile for Inference: INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 628122 INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 135087 -INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 62870 -INFO - NPU ACTIVE cycles: 1081007 -INFO - NPU IDLE cycles: 626 -INFO - NPU TOTAL cycles: 1081634 -INFO - CPU ACTIVE cycles (approx): 993553 +... INFO - Time ms: 210 ``` -- cgit v1.2.1