From d580eee180be219e118152cedabc9637da8574d6 Mon Sep 17 00:00:00 2001 From: alexander Date: Tue, 4 May 2021 21:24:22 +0100 Subject: MLECO-1898: removing support of legacy sse-200 platform Signed-off-by: alexander Change-Id: Ie462e786af1d429bcb815f2c10656ed82862715a --- CMakeLists.txt | 2 +- docs/documentation.md | 1 - docs/sections/building.md | 12 - docs/sections/deployment.md | 17 +- docs/use_cases/ad.md | 30 +-- scripts/cmake/bare-metal-sources.cmake | 4 +- .../subsystem-profiles/corstone-sse-200.cmake | 255 --------------------- scripts/py/gen_fpga_mem_map.py | 14 -- .../bare-metal/bsp/mem_layout/mps3-sse-200.sct | 102 --------- 9 files changed, 26 insertions(+), 411 deletions(-) delete mode 100644 scripts/cmake/subsystem-profiles/corstone-sse-200.cmake delete mode 100644 source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct diff --git a/CMakeLists.txt b/CMakeLists.txt index d434c9e..7bc8d08 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -71,7 +71,7 @@ USER_OPTION(TARGET_PLATFORM "Target platform to execute evaluation application: mps3 STRING) -USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-200, sse-300 or none" +USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-300 or none" sse-300 STRING) diff --git a/docs/documentation.md b/docs/documentation.md index 566feab..ece2f56 100644 --- a/docs/documentation.md +++ b/docs/documentation.md @@ -231,7 +231,6 @@ See: - [Preparing build environment](./sections/building.md#preparing-build-environment) - [Create a build directory](./sections/building.md#create-a-build-directory) - [Configuring the build for `MPS3: SSE-300`](./sections/building.md#configuring-the-build-for-mps3-sse-300) - - [Configuring the build for `MPS3: SSE-200`](./sections/building.md#configuring-the-build-for-mps3-sse-200) - [Configuring native unit-test build](./sections/building.md#configuring-native-unit-test-build) - [Configuring the build for `simple_platform`](./sections/building.md#configuring-the-build-for-simple_platform) - [Building the configured project](./sections/building.md#building-the-configured-project) diff --git a/docs/sections/building.md b/docs/sections/building.md index c53b1f5..c8eef7c 100644 --- a/docs/sections/building.md +++ b/docs/sections/building.md @@ -10,7 +10,6 @@ - [Preparing build environment](#preparing-build-environment) - [Create a build directory](#create-a-build-directory) - [Configuring the build for MPS3: SSE-300](#configuring-the-build-for-mps3-sse-300) - - [Configuring the build for MPS3: SSE-200](#configuring-the-build-for-mps3-sse-200) - [Configuring native unit-test build](#configuring-native-unit-test-build) - [Configuring the build for simple_platform](#configuring-the-build-for-simple_platform) - [Building the configured project](#building-the-configured-project) @@ -122,7 +121,6 @@ The build parameters are: FVP and the MPS3 FPGA, this should be left to the default value of SSE-300: - `sse-300` (default - [Arm® Corstone™-300](https://developer.arm.com/ip-products/subsystem/corstone/corstone-300)) - - `sse-200` - `TENSORFLOW_SRC_PATH`: Path to the root of the TensorFlow directory. The default value points to the TensorFlow submodule in the @@ -331,15 +329,6 @@ cmake \ > **Note:** If re-building with changed parameters values, it is highly advised to clean the build directory and re-run the CMake command. -### Configuring the build for MPS3: SSE-200 - -```commandline -cmake \ - -DTARGET_PLATFORM=mps3 \ - -DTARGET_SUBSYSTEM=sse-200 \ - -DCMAKE_TOOLCHAIN_FILE=scripts/cmake/bare-metal-toolchain.cmake .. -``` - ### Configuring native unit-test build ```commandline @@ -771,7 +760,6 @@ scripts/ ├── cmake │ ├── ... │ ├── subsystem-profiles -│ │ ├── corstone-sse-200.cmake │ │ └── corstone-sse-300.cmake │ ├── templates │ │ ├── mem_regions.h.template diff --git a/docs/sections/deployment.md b/docs/sections/deployment.md index 4c9101c..a6e9c3c 100644 --- a/docs/sections/deployment.md +++ b/docs/sections/deployment.md @@ -2,11 +2,13 @@ ## Contents -- [Fixed Virtual Platform](#fixed-virtual-platform) - - [Setting up the MPS3 Arm Corstone-300 FVP](#setting-up-the-mps3-arm-corstone-300-fvp) - - [Deploying on an FVP emulating MPS3](#deploying-on-an-fvp-emulating-mps3) -- [MPS3 board](#mps3-board) - - [Deployment on MPS3 board](#deployment-on-mps3-board) +- [Deployment](#deployment) + - [Contents](#contents) + - [Fixed Virtual Platform](#fixed-virtual-platform) + - [Setting up the MPS3 Arm Corstone-300 FVP](#setting-up-the-mps3-arm-corstone-300-fvp) + - [Deploying on an FVP emulating MPS3](#deploying-on-an-fvp-emulating-mps3) + - [MPS3 board](#mps3-board) + - [Deployment on MPS3 board](#deployment-on-mps3-board) The sample application for Arm® Ethos™-U55 can be deployed on two target platforms, both of which implement the Arm® Corstone™-300 design (see @@ -25,9 +27,6 @@ Download the correct archive from the list under `Arm Corstone-300`. We need the - Emulates MPS3 board (not for MPS2 FPGA board) - Contains support for Arm® Ethos™-U55 -> **Note:** Currently, the FVP only has a Linux OS version. Also, there are no FVPs available for `SSE-200` -> which satisfy the above conditions. - For FVP, the elf or the axf file can be run using the Fast Model executable as outlined under the [Starting Fast Model simulation](./setup.md/#starting-fast-model-simulation) except for the binary being pointed at here @@ -142,7 +141,7 @@ For more information on getting started with an MPS3 board, please refer to ### Deployment on MPS3 board > **NOTE**: These instructions are valid only if the evaluation is being - done using the MPS3 FPGA platform using either `SSE-200` or `SSE-300`. + done using the MPS3 FPGA platform using `SSE-300`. To run the application on MPS3 platform, firstly it's necessary to make sure that the platform has been set up using the correct configuration. diff --git a/docs/use_cases/ad.md b/docs/use_cases/ad.md index 82da9e5..5a37a0a 100644 --- a/docs/use_cases/ad.md +++ b/docs/use_cases/ad.md @@ -1,19 +1,19 @@ # Anomaly Detection Code Sample -- [Introduction](#introduction) - - [Prerequisites](#prerequisites) -- [Building the code sample application from sources](#building-the-code-sample-application-from-sources) - - [Build options](#build-options) - - [Build process](#build-process) - - [Add custom input](#add-custom-input) - - [Add custom model](#add-custom-model) -- [Setting-up and running Ethos-U55 Code Sample](#setting-up-and-running-ethos-u55-code-sample) - - [Setting up the Ethos-U55 Fast Model](#setting-up-the-ethos-u55-fast-model) - - [Starting Fast Model simulation](#starting-fast-model-simulation) - - [Running Anomaly Detection](#running-anomaly-detection) -- [Anomaly Detection processing information](#anomaly-detection-processing-information) - - [Preprocessing and feature extraction](#preprocessing-and-feature-extraction) - - [Postprocessing](#postprocessing) +- [Anomaly Detection Code Sample](#anomaly-detection-code-sample) + - [Introduction](#introduction) + - [Preprocessing and feature extraction](#preprocessing-and-feature-extraction) + - [Postprocessing](#postprocessing) + - [Prerequisites](#prerequisites) + - [Building the code sample application from sources](#building-the-code-sample-application-from-sources) + - [Build options](#build-options) + - [Build process](#build-process) + - [Add custom input](#add-custom-input) + - [Add custom model](#add-custom-model) + - [Setting-up and running Ethos-U55 Code Sample](#setting-up-and-running-ethos-u55-code-sample) + - [Setting up the Ethos-U55 Fast Model](#setting-up-the-ethos-u55-fast-model) + - [Starting Fast Model simulation](#starting-fast-model-simulation) + - [Running Anomaly Detection](#running-anomaly-detection) ## Introduction @@ -296,7 +296,7 @@ The log from the configuration stage should tell you what model path has been us After compiling, your custom model will have now replaced the default one in the application. >**Note:** In order to successfully run the model, the NPU needs to be enabled and - the platform `TARGET_PLATFORM` is set to mps3 and TARGET_SUBSYSTEM is SSE-200 or SSE-300. + the platform `TARGET_PLATFORM` is set to `mps3` and `TARGET_SUBSYSTEM` is `SSE-300`. ## Setting-up and running Ethos-U55 Code Sample diff --git a/scripts/cmake/bare-metal-sources.cmake b/scripts/cmake/bare-metal-sources.cmake index 3e24d7b..8b348e3 100644 --- a/scripts/cmake/bare-metal-sources.cmake +++ b/scripts/cmake/bare-metal-sources.cmake @@ -48,10 +48,10 @@ if (TARGET_PLATFORM STREQUAL mps3) # TARGET_SUBSYSTEM either should have been defined by the user or set to a default value if (NOT DEFINED TARGET_SUBSYSTEM) message(FATAL_ERROR "Target subsystem for mps3 undefined, " - "specify -DTARGET_SUBSYSTEM=") + "specify -DTARGET_SUBSYSTEM=") endif () - if (TARGET_SUBSYSTEM STREQUAL sse-200 OR TARGET_SUBSYSTEM STREQUAL sse-300) + if (TARGET_SUBSYSTEM STREQUAL sse-300) message(STATUS "target subsystem is ${TARGET_SUBSYSTEM}") set(BSP_PACKAGE_DIR "${PLAT_HAL}/bsp/bsp-packs/mps3") set(SCAT_FILE "${PLAT_HAL}/bsp/mem_layout/mps3-${TARGET_SUBSYSTEM}.sct") diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-200.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-200.cmake deleted file mode 100644 index 8e2cd98..0000000 --- a/scripts/cmake/subsystem-profiles/corstone-sse-200.cmake +++ /dev/null @@ -1,255 +0,0 @@ -#---------------------------------------------------------------------------- -# Copyright (c) 2021 Arm Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -#---------------------------------------------------------------------------- - -# CMake configuration file for peripheral memory map for MPS3 as per SSE-200 design -################################################################################################### -# Application specific config # -################################################################################################### - -# This parameter is based on the linker/scatter script for SSE-200. Do not change this parameter -# in isolation. -set(ACTIVATION_BUF_SRAM_SZ "0x00200000" CACHE STRING "Maximum SRAM size for activation buffers") -set(DESIGN_NAME "SSE-200" CACHE STRING "Design name") -################################################################################################### -# Mem sizes # -################################################################################################### -set(ITCM_SIZE "0x00100000" CACHE STRING "ITCM size: 1 MiB") -set(DTCM_BLK_SIZE "0x00100000" CACHE STRING "DTCM size: 1 MiB, 4 banks") -set(BRAM_SIZE "0x00200000" CACHE STRING "BRAM size: 2 MiB") -set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB") -set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB") - -################################################################################################### -# Base addresses # -################################################################################################### -set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address") -set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address") -set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address") -set(DTCM1_BASE_NS "0x20100000" CACHE STRING "Data TCM block 1 Non-Secure base address") -set(DTCM2_BASE_NS "0x20200000" CACHE STRING "Data TCM block 2 Non-Secure base address") -set(DTCM3_BASE_NS "0x20300000" CACHE STRING "Data TCM block 3 Non-Secure base address") -set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address") -set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address") -set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address") -set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address") -set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address") - -set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address") -set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address") -set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address") -set(DTCM1_BASE_S "0x30100000" CACHE STRING "Data TCM block 1 Secure base address") -set(DTCM2_BASE_S "0x30200000" CACHE STRING "Data TCM block 2 Secure base address") -set(DTCM3_BASE_S "0x30300000" CACHE STRING "Data TCM block 3 Secure base address") -set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address") -set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address") -set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address") -set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address") - -set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address") -set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address") -set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address") -set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address") - -if (ETHOS_U55_ENABLED) - set(ETHOS_U55_BASE "0x41700000" CACHE STRING "Ethos-U55 base address") - set(ETHOS_U55_TA0_BASE "0x41701000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(ETHOS_U55_TA1_BASE "0x41701200" CACHE STRING "Ethos-U55's timing adapter 1 base address") -endif () - -set(MPS3_I2C0_BASE "0x41200000" CACHE STRING "Touch Screen I2C Base Address ") -set(MPS3_I2C1_BASE "0x41201000" CACHE STRING "Audio Interface I2C Base Address ") -set(MPS3_SSP2_BASE "0x41202000" CACHE STRING "ADC SPI PL022 Base Address") -set(MPS3_SSP3_BASE "0x41203000" CACHE STRING "Shield 0 SPI PL022 Base Address") - -set(MPS3_SSP4_BASE "0x41204000" CACHE STRING "Shield 1 SPI PL022 Base Address") -set(MPS3_I2C2_BASE "0x41205000" CACHE STRING "Shield 0 SBCon Base Address ") -set(MPS3_I2C3_BASE "0x41206000" CACHE STRING "Shield 1 SBCon Base Address ") - -set(MPS3_I2C4_BASE "0x41207000" CACHE STRING "HDMI I2C SBCon Base Address ") -set(MPS3_I2C5_BASE "0x41208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ") -set(MPS3_SCC_BASE "0x41300000" CACHE STRING "SCC Base Address ") -set(MPS3_AAIC_I2S_BASE "0x41301000" CACHE STRING "Audio Interface I2S Base Address ") -set(MPS3_FPGAIO_BASE "0x41302000" CACHE STRING "FPGA IO Base Address ") -set(CMSDK_UART0_BASE "0x41303000" CACHE STRING "UART 0 Base Address ") -set(CMSDK_UART1_BASE "0x41304000" CACHE STRING "UART 1 Base Address ") -set(CMSDK_UART2_BASE "0x41305000" CACHE STRING "UART 2 Base Address ") -set(CMSDK_UART3_BASE "0x41306000" CACHE STRING "UART 3 Base Address Shield 0") - -set(CMSDK_UART4_BASE "0x41307000" CACHE STRING "UART 4 Base Address Shield 1") -set(CMSDK_UART5_BASE "0x41308000" CACHE STRING "UART 5 Base Address ") -set(HDMI_AUDIO_BASE "0x41309000" CACHE STRING "HDMI AUDIO Base Address ") -set(CLCD_CONFIG_BASE "0x4130A000" CACHE STRING "CLCD CONFIG Base Address ") -set(RTC_BASE "0x4130B000" CACHE STRING "RTC Base address ") -set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address ") -set(USB_BASE "0x41500000" CACHE STRING "USB Base Address ") - -set(MPS3_eMMC_BASE "0x41702000" CACHE STRING "User eMMC Base Address") -set(USER_BASE "0x41703000" CACHE STRING "User ? Base Address ") - -set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ") -set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ") - -set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address") -set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 0 Base Address") -set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 0 Base Address") -set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 0 Base Address") - -set(SEC_MPS3_I2C0_BASE "0x51200000" CACHE STRING "Touch Screen I2C Base Address ") -set(SEC_MPS3_I2C1_BASE "0x51201000" CACHE STRING "Audio Interface I2C Base Address ") -set(SEC_MPS3_SSP2_BASE "0x51202000" CACHE STRING "ADC SPI PL022 Base Address") -set(SEC_MPS3_SSP3_BASE "0x51203000" CACHE STRING "Shield 0 SPI PL022 Base Address") - -set(SEC_MPS3_SSP4_BASE "0x51204000" CACHE STRING "Shield 1 SPI PL022 Base Address") -set(SEC_MPS3_I2C2_BASE "0x51205000" CACHE STRING "Shield 0 SBCon Base Address ") -set(SEC_MPS3_I2C3_BASE "0x51206000" CACHE STRING "Shield 1 SBCon Base Address ") - -set(SEC_MPS3_I2C4_BASE "0x51207000" CACHE STRING "HDMI I2C SBCon Base Address ") -set(SEC_MPS3_I2C5_BASE "0x51208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ") -set(SEC_MPS3_SCC_BASE "0x51300000" CACHE STRING "SCC Base Address ") -set(SEC_MPS3_AAIC_I2S_BASE "0x51301000" CACHE STRING "Audio Interface I2S Base Address ") -set(SEC_MPS3_FPGAIO_BASE "0x51302000" CACHE STRING "FPGA IO Base Address ") -set(SEC_CMSDK_UART0_BASE "0x51303000" CACHE STRING "UART 0 Base Address ") -set(SEC_CMSDK_UART1_BASE "0x51304000" CACHE STRING "UART 1 Base Address ") -set(SEC_CMSDK_UART2_BASE "0x51305000" CACHE STRING "UART 2 Base Address ") -set(SEC_CMSDK_UART3_BASE "0x51306000" CACHE STRING "UART 3 Base Address Shield 0") - -set(SEC_CMSDK_UART4_BASE "0x51307000" CACHE STRING "UART 4 Base Address Shield 1") -set(SEC_CMSDK_UART5_BASE "0x51308000" CACHE STRING "UART 5 Base Address ") -set(SEC_HDMI_AUDIO_BASE "0x51309000" CACHE STRING "HDMI AUDIO Base Address ") -set(SEC_CLCD_CONFIG_BASE "0x5130A000" CACHE STRING "CLCD CONFIG Base Address ") -set(SEC_RTC_BASE "0x5130B000" CACHE STRING "RTC Base address ") -set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address ") -set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address ") - -if (ETHOS_U55_ENABLED) - set(SEC_ETHOS_U55_BASE "0x51700000" CACHE STRING "Ethos-U55 base address") - set(SEC_ETHOS_U55_TA0_BASE "0x51701000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(SEC_ETHOS_U55_TA1_BASE "0x51701200" CACHE STRING "Ethos-U55's timing adapter 1 base address") -endif () - -set(SEC_MMC_BASE "0x51702000" CACHE STRING "User eMMC Base Address") -set(SEC_USER_BASE "0x51703000" CACHE STRING "User ? Base Address ") - -set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ") -set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ") - -################################################################################################### -# IRQ numbers # -################################################################################################### -set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt") -set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ") -set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K Timer Interrupt ") -set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ") -set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ") -set(DUALTIMER_IRQn " 5" CACHE STRING " Dual Timer Interrupt ") -set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ") -set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ") -set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ") -set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ") - -set(UARTRX0_IRQn "32" CACHE STRING " UART 0 RX Interrupt ") -set(UARTTX0_IRQn "33" CACHE STRING " UART 0 TX Interrupt ") -set(UARTRX1_IRQn "34" CACHE STRING " UART 1 RX Interrupt ") -set(UARTTX1_IRQn "35" CACHE STRING " UART 1 TX Interrupt ") -set(UARTRX2_IRQn "36" CACHE STRING " UART 2 RX Interrupt ") -set(UARTTX2_IRQn "37" CACHE STRING " UART 2 TX Interrupt ") -set(UARTRX3_IRQn "38" CACHE STRING " UART 3 RX Interrupt ") -set(UARTTX3_IRQn "39" CACHE STRING " UART 3 TX Interrupt ") -set(UARTRX4_IRQn "40" CACHE STRING " UART 4 RX Interrupt ") -set(UARTTX4_IRQn "41" CACHE STRING " UART 4 TX Interrupt ") -set(UART0_IRQn "42" CACHE STRING " UART 0 combined Interrupt ") -set(UART1_IRQn "43" CACHE STRING " UART 1 combined Interrupt ") -set(UART2_IRQn "44" CACHE STRING " UART 2 combined Interrupt ") -set(UART3_IRQn "45" CACHE STRING " UART 3 combined Interrupt ") -set(UART4_IRQn "46" CACHE STRING " UART 4 combined Interrupt ") -set(UARTOVF_IRQn "47" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ") -set(ETHERNET_IRQn "48" CACHE STRING " Ethernet Interrupt ") -set(I2S_IRQn "49" CACHE STRING " I2S Interrupt ") -set(TSC_IRQn "50" CACHE STRING " Touch Screen Interrupt ") -set(SPI2_IRQn "52" CACHE STRING " SPI 2 Interrupt ") -set(SPI3_IRQn "53" CACHE STRING " SPI 3 Interrupt ") -set(SPI4_IRQn "54" CACHE STRING " SPI 4 Interrupt ") - -if (ETHOS_U55_ENABLED) - if (CPU_CORTEX_M55 EQUAL 1) - set(EthosU_IRQn "55" CACHE STRING " Ethos-U55 Interrupt ") - elseif (CPU_CORTEX_M33 EQUAL 1) - set(EthosU_IRQn "67" CACHE STRING " Ethos-U55 Interrupt ") - endif() -endif () - -set(GPIO0_IRQn "68" CACHE STRING " GPIO 0 Combined Interrupt ") -set(GPIO1_IRQn "69" CACHE STRING " GPIO 1 Combined Interrupt ") -set(GPIO2_IRQn "70" CACHE STRING " GPIO 2 Combined Interrupt ") -set(GPIO3_IRQn "71" CACHE STRING " GPIO 3 Combined Interrupt ") - -set(GPIO0_0_IRQn "72" CACHE STRING "") -set(GPIO0_1_IRQn "73" CACHE STRING "") -set(GPIO0_2_IRQn "74" CACHE STRING "") -set(GPIO0_3_IRQn "75" CACHE STRING "") -set(GPIO0_4_IRQn "76" CACHE STRING "") -set(GPIO0_5_IRQn "77" CACHE STRING "") -set(GPIO0_6_IRQn "78" CACHE STRING "") -set(GPIO0_7_IRQn "79" CACHE STRING "") -set(GPIO0_8_IRQn "80" CACHE STRING "") -set(GPIO0_9_IRQn "81" CACHE STRING "") -set(GPIO0_10_IRQn "82" CACHE STRING "") -set(GPIO0_11_IRQn "83" CACHE STRING "") -set(GPIO0_12_IRQn "84" CACHE STRING "") -set(GPIO0_13_IRQn "85" CACHE STRING "") -set(GPIO0_14_IRQn "86" CACHE STRING "") -set(GPIO0_15_IRQn "87" CACHE STRING "") -set(GPIO1_0_IRQn "88" CACHE STRING "") -set(GPIO1_1_IRQn "89" CACHE STRING "") -set(GPIO1_2_IRQn "90" CACHE STRING "") -set(GPIO1_3_IRQn "91" CACHE STRING "") -set(GPIO1_4_IRQn "92" CACHE STRING "") -set(GPIO1_5_IRQn "93" CACHE STRING "") -set(GPIO1_6_IRQn "94" CACHE STRING "") -set(GPIO1_7_IRQn "95" CACHE STRING "") -set(GPIO1_8_IRQn "96" CACHE STRING "") -set(GPIO1_9_IRQn "97" CACHE STRING "") -set(GPIO1_10_IRQn "98" CACHE STRING "") -set(GPIO1_11_IRQn "99" CACHE STRING "") -set(GPIO1_12_IRQn "100" CACHE STRING "") -set(GPIO1_13_IRQn "101" CACHE STRING "") -set(GPIO1_14_IRQn "102" CACHE STRING "") -set(GPIO1_15_IRQn "103" CACHE STRING "") -set(GPIO2_0_IRQn "104" CACHE STRING "") -set(GPIO2_1_IRQn "105" CACHE STRING "") -set(GPIO2_2_IRQn "106" CACHE STRING "") -set(GPIO2_3_IRQn "107" CACHE STRING "") -set(GPIO2_4_IRQn "108" CACHE STRING "") -set(GPIO2_5_IRQn "109" CACHE STRING "") -set(GPIO2_6_IRQn "110" CACHE STRING "") -set(GPIO2_7_IRQn "111" CACHE STRING "") -set(GPIO2_8_IRQn "112" CACHE STRING "") -set(GPIO2_9_IRQn "113" CACHE STRING "") -set(GPIO2_10_IRQn "114" CACHE STRING "") -set(GPIO2_11_IRQn "115" CACHE STRING "") -set(GPIO2_12_IRQn "116" CACHE STRING "") -set(GPIO2_13_IRQn "117" CACHE STRING "") -set(GPIO2_14_IRQn "118" CACHE STRING "") -set(GPIO2_15_IRQn "119" CACHE STRING "") -set(GPIO3_0_IRQn "120" CACHE STRING "") -set(GPIO3_1_IRQn "121" CACHE STRING "") -set(GPIO3_2_IRQn "122" CACHE STRING "") -set(GPIO3_3_IRQn "123" CACHE STRING "") -set(UARTRX5_IRQn "124" CACHE STRING "UART 5 RX Interrupt") -set(UARTTX5_IRQn "125" CACHE STRING "UART 5 TX Interrupt") -set(UART5_IRQn "126" CACHE STRING "UART 5 combined Interrupt") -set(HDCLCD_IRQn "127" CACHE STRING "HDCLCD Interrupt") diff --git a/scripts/py/gen_fpga_mem_map.py b/scripts/py/gen_fpga_mem_map.py index 6a2d1d2..5703a8d 100644 --- a/scripts/py/gen_fpga_mem_map.py +++ b/scripts/py/gen_fpga_mem_map.py @@ -50,20 +50,6 @@ class TargetSubsystem: """ # Dict with mem map and binary names we expect self.subsystems = { - "sse-200": { - "mmap_mcc" : { - # FPGA addr | MCC addr | - "0x00000000": "0x00000000", # ITCM (NS) - "0x10000000": "0x01000000", # ITCM (S) - "0x20000000": "0x02000000", # DTCM (NS) - "0x30000000": "0x03000000", # DTCM (S) - "0x60000000": "0x08000000" # DDR (NS) - }, - "bin_names": { - 0: "itcm.bin", - 1: "dram.bin" - } - }, "sse-300": { "mmap_mcc" : { # FPGA addr | MCC addr | diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct deleted file mode 100644 index 293193e..0000000 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct +++ /dev/null @@ -1,102 +0,0 @@ -; Copyright (c) 2021 Arm Limited. All rights reserved. -; SPDX-License-Identifier: Apache-2.0 -; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - -; ************************************************************* -; *** Scatter-Loading Description File *** -; ************************************************************* -; -; Sections used: -;--------------------------------------------------------- -; | Start | End | Size | Remarks | -;-|-------------|-------------|-------------|------------| -; | 0x0000_0000 | 0x0010_0000 | 0x0010_0000 | ITCM (RO) | -; | 0x0010_0000 | 0x0030_0000 | 0x0020_0000 | BRAM (RW) | -; | 0x2000_0000 | 0x2040_0000 | 0x0040_0000 | DTCM (RW) | -; | 0x6000_0000 | 0x6200_0000 | 0x0200_0000 | DRAM (RW) | -;-|-------------|-------------|-------------|------------| -; ITCM is aliased at 0x1000_0000 (single bank) -; BRAM is aliased at 0x1010_0000 -; DTCM is aliased at 0x3000_0000 (four banks of 1MiB each) -; DRAM is aliased at 0x7000_0000 (section is 256MiB) -; -; Note: Ethos-U55 can only access DRAM and BRAM sections -;--------------------------------------------------------- -; First load region -;--------------------------------------------------------- -LOAD_REGION_0 0x00000000 0x00100000 -{ - ;----------------------------------------------------- - ; First part of code mem - 1MiB - ;----------------------------------------------------- - itcm.bin 0x00000000 0x00100000 - { - *.o (RESET, +First) - * (InRoot$$Sections) - .ANY (+RO) - } - - ;----------------------------------------------------- - ; Code memory's 2MiB - reserved for activation buffers - ; Make sure this is uninitialised. - ;----------------------------------------------------- - bram.bin 0x00100000 UNINIT 0x00200000 - { - ; activation buffers a.k.a tensor arena - *.o (.bss.NoInit.activation_buf) - } - - ;----------------------------------------------------- - ; 1MiB bank is used for any other RW or ZI data - ; Note: this region is internal to the Cortex-M CPU - ;----------------------------------------------------- - dtcm.bin 0x20000000 0x00100000 - { - .ANY(+RW +ZI) - } - - ;----------------------------------------------------- - ; 128kiB of stack space within SRAM region - ;----------------------------------------------------- - ARM_LIB_STACK 0x20100000 EMPTY ALIGN 8 0x00020000 - {} - - ;----------------------------------------------------- - ; 2MiB of heap space within the SRAM region - ;----------------------------------------------------- - ARM_LIB_HEAP 0x20200000 EMPTY ALIGN 8 0x00200000 - {} -} - -;--------------------------------------------------------- -; Second load region -;--------------------------------------------------------- -LOAD_REGION_1 0x60000000 0x02000000 -{ - ;----------------------------------------------------- - ; 32 MiB of DRAM space for nn model and input vectors - ;----------------------------------------------------- - dram.bin 0x60000000 0x02000000 - { - ; nn model's baked in input matrices - *.o (ifm) - - ; nn model - *.o (nn_model) - - ; if the activation buffer (tensor arena) doesn't - ; fit in the SRAM region, we accommodate it here - *.o (activation_buf) - } -} -- cgit v1.2.1