From a1256e3881d1ec3e77b341dbb0c5c5dbf7ab3247 Mon Sep 17 00:00:00 2001 From: Kshitij Sisodia Date: Wed, 23 Feb 2022 14:40:45 +0000 Subject: MLECO-2948: Minor refactoring for platform modules. Reducing dependency on cmsis-device sources as these will be removed under MLECO-2944. Also, starting to refactor to allow HAL to drop NPU and TA init routines - this will happen in future CRs. Added platform driver for native, and subsequent patches will attempt to get rid of the HAL "profile" specific sources and allow platform stub implementations at a level below HAL. This will allow platforms drivers to only override the range of functions that they actually want to implement and will fall back on stubs for the rest. In this CR only "utils" have been removed. Change-Id: I09b4a28e20847a07a956c818c6f47c74aab89063 --- CMakeLists.txt | 2 +- .../platforms/native/build_configuration.cmake | 1 + source/hal/CMakeLists.txt | 37 +- source/hal/cmsis_device/include/irqs.h | 13 - source/hal/cmsis_device/source/irqs.c | 53 +- source/hal/hal.c | 17 +- source/hal/include/hal.h | 3 +- source/hal/platform/mps3/CMakeLists.txt | 29 +- source/hal/platform/mps3/include/device_mps3.h | 113 ---- .../hal/platform/mps3/include/platform_drivers.h | 41 +- source/hal/platform/mps3/include/smm_mps3.h | 615 -------------------- source/hal/platform/mps3/include/timer_mps3.h | 12 +- source/hal/platform/mps3/source/device_mps3.c | 6 +- .../hal/platform/mps3/source/include/device_mps3.h | 112 ++++ source/hal/platform/mps3/source/include/smm_mps3.h | 616 +++++++++++++++++++++ source/hal/platform/mps3/source/platform_drivers.c | 131 +++++ source/hal/platform/mps3/source/timer_mps3.c | 64 ++- source/hal/platform/native/CMakeLists.txt | 56 ++ .../hal/platform/native/include/platform_drivers.h | 41 ++ .../hal/platform/native/source/platform_drivers.c | 33 ++ source/hal/platform/simple/CMakeLists.txt | 3 +- .../hal/platform/simple/include/platform_drivers.h | 36 +- source/hal/platform/simple/include/stubs/glcd.h | 12 +- .../simple/include/timer_simple_platform.h | 7 +- .../hal/platform/simple/source/platform_drivers.c | 45 ++ source/hal/platform/simple/source/stubs_glcd.c | 9 +- .../platform/simple/source/timer_simple_platform.c | 71 ++- .../bare-metal/data_acquisition/data_acq.c | 5 +- .../bare-metal/data_presentation/lcd/lcd_img.c | 1 + .../hal/profiles/bare-metal/timer/platform_timer.c | 3 +- .../bare-metal/utils/include/system_init.h | 43 -- source/hal/profiles/bare-metal/utils/system_init.c | 114 ---- .../profiles/native/utils/include/system_init.h | 38 -- source/hal/profiles/native/utils/system_init.c | 32 -- source/profiler/CMakeLists.txt | 5 + 35 files changed, 1312 insertions(+), 1107 deletions(-) delete mode 100644 source/hal/platform/mps3/include/device_mps3.h delete mode 100644 source/hal/platform/mps3/include/smm_mps3.h create mode 100644 source/hal/platform/mps3/source/include/device_mps3.h create mode 100644 source/hal/platform/mps3/source/include/smm_mps3.h create mode 100644 source/hal/platform/mps3/source/platform_drivers.c create mode 100644 source/hal/platform/native/CMakeLists.txt create mode 100644 source/hal/platform/native/include/platform_drivers.h create mode 100644 source/hal/platform/native/source/platform_drivers.c create mode 100644 source/hal/platform/simple/source/platform_drivers.c delete mode 100644 source/hal/profiles/bare-metal/utils/include/system_init.h delete mode 100644 source/hal/profiles/bare-metal/utils/system_init.c delete mode 100644 source/hal/profiles/native/utils/include/system_init.h delete mode 100644 source/hal/profiles/native/utils/system_init.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 14ec1aa..bbd7756 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -236,4 +236,4 @@ foreach(use_case ${USE_CASES}) endforeach() -print_useroptions() \ No newline at end of file +print_useroptions() diff --git a/scripts/cmake/platforms/native/build_configuration.cmake b/scripts/cmake/platforms/native/build_configuration.cmake index bc91804..63f9491 100644 --- a/scripts/cmake/platforms/native/build_configuration.cmake +++ b/scripts/cmake/platforms/native/build_configuration.cmake @@ -22,6 +22,7 @@ function(set_platform_global_defaults) CACHE FILEPATH "Toolchain file") endif() + set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/native" PARENT_SCOPE) set(TEST_TPIP ${DOWNLOAD_DEP_DIR}/test) file(MAKE_DIRECTORY ${TEST_TPIP}) diff --git a/source/hal/CMakeLists.txt b/source/hal/CMakeLists.txt index ea19de5..0d844b2 100644 --- a/source/hal/CMakeLists.txt +++ b/source/hal/CMakeLists.txt @@ -43,8 +43,7 @@ set(PLATFORM_PROFILE_DIR profiles/${PLATFORM_PROFILE}) target_include_directories(${HAL_TARGET} PUBLIC include - ${PLATFORM_PROFILE_DIR}/timer/include - ${PLATFORM_PROFILE_DIR}/utils/include) + ${PLATFORM_PROFILE_DIR}/timer/include) ## Common sources for all profiles target_sources(${HAL_TARGET} @@ -52,8 +51,7 @@ target_sources(${HAL_TARGET} hal.c ${PLATFORM_PROFILE_DIR}/data_presentation/data_psn.c ${PLATFORM_PROFILE_DIR}/data_acquisition/data_acq.c - ${PLATFORM_PROFILE_DIR}/timer/platform_timer.c - ${PLATFORM_PROFILE_DIR}/utils/system_init.c) + ${PLATFORM_PROFILE_DIR}/timer/platform_timer.c) if (DEFINED VERIFY_TEST_OUTPUT) message(STATUS "Test output verification flag is: ${VERIFY_TEST_OUTPUT}") @@ -61,13 +59,14 @@ if (DEFINED VERIFY_TEST_OUTPUT) VERIFY_TEST_OUTPUT=${VERIFY_TEST_OUTPUT}) endif () +if (NOT DEFINED PLATFORM_DRIVERS_DIR) + message(FATAL_ERROR "PLATFORM_DRIVERS_DIR need to be defined for this target") +endif() + + ############################ bare-metal profile ############################# if (PLATFORM_PROFILE STREQUAL bare-metal) - if (NOT DEFINED PLATFORM_DRIVERS_DIR) - message(FATAL_ERROR "PLATFORM_DRIVERS_DIR need to be defined for this target") - endif() - ## Additional include directories - public target_include_directories(${HAL_TARGET} PUBLIC @@ -96,15 +95,6 @@ if (PLATFORM_PROFILE STREQUAL bare-metal) # Add dependencies for platform_driver first, in case they are needed by it. add_subdirectory(cmsis_device ${CMAKE_BINARY_DIR}/cmsis_device) - # Add platform-drivers target - add_subdirectory(${PLATFORM_DRIVERS_DIR} ${CMAKE_BINARY_DIR}/platform_driver) - - # Link time library targets: - target_link_libraries(${HAL_TARGET} - PUBLIC - log - platform-drivers) - # If Ethos-U is enabled, we need the driver library too if (ETHOS_U_NPU_ENABLED) @@ -172,6 +162,7 @@ if (PLATFORM_PROFILE STREQUAL bare-metal) ############################ native profile ############################# elseif (PLATFORM_PROFILE STREQUAL native) + ## Additional include directories - private target_include_directories(${HAL_TARGET} PRIVATE @@ -187,12 +178,16 @@ elseif (PLATFORM_PROFILE STREQUAL native) PUBLIC PLATFORM_HAL=PLATFORM_UNKNOWN_LINUX_OS ACTIVATION_BUF_SRAM_SZ=0) +endif() - target_link_libraries(${HAL_TARGET} - PUBLIC - log) +# Add platform-drivers target +add_subdirectory(${PLATFORM_DRIVERS_DIR} ${CMAKE_BINARY_DIR}/platform_driver) -endif() +# Link time library targets: +target_link_libraries(${HAL_TARGET} + PUBLIC + log + platform-drivers) # Display status: message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) diff --git a/source/hal/cmsis_device/include/irqs.h b/source/hal/cmsis_device/include/irqs.h index 5ddda97..234edd7 100644 --- a/source/hal/cmsis_device/include/irqs.h +++ b/source/hal/cmsis_device/include/irqs.h @@ -32,19 +32,6 @@ typedef void (*const irq_vec_type)(void); **/ extern void Reset_Handler(void); -/** - * @brief Gets the system tick triggered cycle counter for the CPU. - * @return 64-bit counter value. - **/ -extern uint64_t Get_SysTick_Cycle_Count(void); - -/** - * @brief Initialises the system tick registers. - * @return Error code return from sys tick configuration function - * (0 = no error). - **/ -extern int Init_SysTick(void); - #ifdef __cplusplus } #endif diff --git a/source/hal/cmsis_device/source/irqs.c b/source/hal/cmsis_device/source/irqs.c index 7d8aa06..2ecd4d5 100644 --- a/source/hal/cmsis_device/source/irqs.c +++ b/source/hal/cmsis_device/source/irqs.c @@ -25,8 +25,6 @@ extern "C" #include #include -static uint64_t cpu_cycle_count = 0; - /** * External references */ @@ -165,24 +163,9 @@ __attribute__((weak)) void PendSV_Handler(void) /** * @brief System tick interrupt handler. **/ -void SysTick_Handler(void) -{ - /* Increment the cycle counter based on load value. */ - cpu_cycle_count += SysTick->LOAD + 1; -} - -/** - * Gets the current SysTick derived counter value - */ -uint64_t Get_SysTick_Cycle_Count(void) +__attribute__((weak)) void SysTick_Handler(void) { - uint32_t systick_val; - - NVIC_DisableIRQ(SysTick_IRQn); - systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk; - NVIC_EnableIRQ(SysTick_IRQn); - - return cpu_cycle_count + (SysTick->LOAD - systick_val); + DEFAULT_IRQ_HANDLER_CALL(); } /** @@ -218,44 +201,12 @@ irq_vec_type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 112 - 128 */ }; -/** - * SysTick initialisation - */ -int Init_SysTick(void) -{ - const uint32_t ticks_10ms = GetSystemCoreClock()/100 + 1; - int err = 0; - - /* Reset CPU cycle count value. */ - cpu_cycle_count = 0; - - /* Changing configuration for sys tick => guard from being - * interrupted. */ - NVIC_DisableIRQ(SysTick_IRQn); - - /* SysTick init - this will enable interrupt too. */ - err = SysTick_Config(ticks_10ms); - - /* Enable interrupt again. */ - NVIC_EnableIRQ(SysTick_IRQn); - - /* Wait for SysTick to kick off */ - while (!err && !SysTick->VAL) { - __NOP(); - } - - return err; -} - /* Reset handler - starting point of our application. */ __attribute__((used)) void Reset_Handler(void) { /* Initialise system. */ SystemInit(); - /* Configure the system tick. */ - Init_SysTick(); - /* cmsis supplied entry point. */ __PROGRAM_START(); } diff --git a/source/hal/hal.c b/source/hal/hal.c index ff470d5..d78ac95 100644 --- a/source/hal/hal.c +++ b/source/hal/hal.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,14 +14,15 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#include "hal.h" /* API */ +#include "hal.h" /* API */ -#include "hal_config.h" /* HAL configuration */ -#include "system_init.h" -#include "log_macros.h" +#include "hal_config.h" /* HAL configuration */ +#include "platform_drivers.h" /* Platform drivers */ +#include "log_macros.h" /* Logging macros */ #include #include +#include #if defined(ARM_NPU) @@ -71,9 +72,9 @@ int hal_init(hal_platform* platform, data_acq_module* data_acq, platform->data_acq = data_acq; platform->data_psn = data_psn; platform->timer = timer; - platform->platform_init = system_init; - platform->platform_release = system_release; - system_name(platform->plat_name, sizeof(platform->plat_name)); + platform->platform_init = platform_init; + platform->platform_release = platform_release; + platform_name(platform->plat_name, sizeof(platform->plat_name)); return 0; } diff --git a/source/hal/include/hal.h b/source/hal/include/hal.h index a192ea7..a535dc9 100644 --- a/source/hal/include/hal.h +++ b/source/hal/include/hal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,7 +23,6 @@ * will also need to be aware of the API exposed by data acquisition and * data presentation modules. */ -#include "hal_config.h" #ifdef __cplusplus extern "C" { diff --git a/source/hal/platform/mps3/CMakeLists.txt b/source/hal/platform/mps3/CMakeLists.txt index 46db2aa..cd95d6c 100644 --- a/source/hal/platform/mps3/CMakeLists.txt +++ b/source/hal/platform/mps3/CMakeLists.txt @@ -70,27 +70,38 @@ target_include_directories(${PLATFORM_DRIVERS_TARGET} include ${SOURCE_GEN_DIR}) +## Include directories - private +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PRIVATE + source/include) + ## Platform sources target_sources(${PLATFORM_DRIVERS_TARGET} PRIVATE source/device_mps3.c - source/timer_mps3.c) + source/timer_mps3.c + source/platform_drivers.c) + +## Directory for additional compnents required by MPS3: +if (NOT DEFINED COMPONENTS_DIR) + set(COMPONENTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../components) +endif() ## Platform component: uart target_sources(${PLATFORM_DRIVERS_TARGET} PRIVATE - ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_cmsdk/uart_cmsdk.c) + ${COMPONENTS_DIR}/uart_cmsdk/uart_cmsdk.c) target_include_directories(${PLATFORM_DRIVERS_TARGET} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/../../components/uart_cmsdk/include) + ${COMPONENTS_DIR}/uart_cmsdk/include) ## Platform component: LCD target_sources(${PLATFORM_DRIVERS_TARGET} PRIVATE - ${CMAKE_CURRENT_SOURCE_DIR}/../../components/lcd_mps3/glcd_mps3.c) + ${COMPONENTS_DIR}/lcd_mps3/glcd_mps3.c) target_include_directories(${PLATFORM_DRIVERS_TARGET} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/../../components/lcd_mps3/include) + ${COMPONENTS_DIR}/lcd_mps3/include) ## This target provides the following definitions for MPS3 specific behaviour ## TODO: We should aim to remove this now with platform refactoring.. @@ -100,13 +111,11 @@ target_compile_definitions(${PLATFORM_DRIVERS_TARGET} ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ} $<$:TIMING_ADAPTER_AVAILABLE>) -# 5. Add dependencies: - +# Add dependencies: target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC - cmsis_device - log) + log cmsis_device) -# 6 Display status: +# Display status: message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR}) message(STATUS "*******************************************************") message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET}) diff --git a/source/hal/platform/mps3/include/device_mps3.h b/source/hal/platform/mps3/include/device_mps3.h deleted file mode 100644 index e0dea1b..0000000 --- a/source/hal/platform/mps3/include/device_mps3.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef DEVICE_MPS3_H -#define DEVICE_MPS3_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "cmsis.h" /* CMSIS device header. */ -#include "smm_mps3.h" /* Memory map for MPS3. */ - -#include - -#define PERIF_CLK (25000000) /* Clock source for APB peripherals */ - -typedef struct _CMSDK_UART_TypeDef_ -{ - __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register. */ - __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register. */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register. */ - - union { - __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register. */ - __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register. */ - }; - __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register. */ - -} CMSDK_UART_TypeDef; - -#define CMSDK_UART0 ((CMSDK_UART_TypeDef *)CMSDK_UART0_BASE) - -/* CMSDK_UART DATA Register Definitions. */ -#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position. */ -#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask. */ - -/* CMSDK_UART STATE Register Definitions. */ -#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position. */ -#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask. */ - -#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position. */ -#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask. */ - -#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position. */ -#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask. */ - -#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position. */ -#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask. */ - -/* CMSDK_UART CTRL Register Definitions. */ -#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position. */ -#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask. */ - -#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position. */ -#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask. */ - -#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position. */ -#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask. */ - -#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position. */ -#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask. */ - -#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position. */ -#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask. */ - -#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position. */ -#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask. */ - -#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position. */ -#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask. */ - -/* CMSDK_UART INTSTATUS\INTCLEAR Register Definitions. */ -#define CMSDK_UART_INT_RXORIRQ_Pos 3 /* CMSDK_UART INT: RXORIRQ Position. */ -#define CMSDK_UART_INT_RXORIRQ_Msk (0x01ul << CMSDK_UART_INT_RXORIRQ_Pos) /* CMSDK_UART INT: RXORIRQ Mask. */ - -#define CMSDK_UART_INT_TXORIRQ_Pos 2 /* CMSDK_UART INT: TXORIRQ Position. */ -#define CMSDK_UART_INT_TXORIRQ_Msk (0x01ul << CMSDK_UART_INT_TXORIRQ_Pos) /* CMSDK_UART INT: TXORIRQ Mask. */ - -#define CMSDK_UART_INT_RXIRQ_Pos 1 /* CMSDK_UART INT: RXIRQ Position. */ -#define CMSDK_UART_INT_RXIRQ_Msk (0x01ul << CMSDK_UART_INT_RXIRQ_Pos) /* CMSDK_UART INT: RXIRQ Mask. */ - -#define CMSDK_UART_INT_TXIRQ_Pos 0 /* CMSDK_UART INT: TXIRQ Position. */ -#define CMSDK_UART_INT_TXIRQ_Msk (0x01ul << CMSDK_UART_INT_TXIRQ_Pos) /* CMSDK_UART INT: TXIRQ Mask. */ - -/* CMSDK_UART BAUDDIV Register Definitions. */ -#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position. */ -#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) - -/** - * @brief Gets the core clock set for MPS3. - * @return Clock value in Hz. - **/ -uint32_t GetMPS3CoreClock(void); - -#ifdef __cplusplus -} -#endif - -#endif /* DEVICE_MPS3_H */ diff --git a/source/hal/platform/mps3/include/platform_drivers.h b/source/hal/platform/mps3/include/platform_drivers.h index c5ed561..156b136 100644 --- a/source/hal/platform/mps3/include/platform_drivers.h +++ b/source/hal/platform/mps3/include/platform_drivers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,15 +15,36 @@ * limitations under the License. */ -#ifndef PLATFORM_DRIVER_H -#define PLATFORM_DRIVER_H +#ifndef PLATFORM_DRIVERS_H +#define PLATFORM_DRIVERS_H -#include "log_macros.h" /* Logging related helpers. */ -#include "uart_stdout.h" /* stdout over UART. */ -#include "smm_mps3.h" /* Mem map for MPS3 peripherals. */ -#include "glcd_mps3.h" /* LCD functions. */ +#include "log_macros.h" /* Logging related helpers. */ + +/* Platform components */ #include "timer_mps3.h" /* Timer functions. */ -#include "device_mps3.h" /* FPGA level definitions and functions. */ -#include "peripheral_irqs.h"/* IRQ numbers for this platform */ +#include "cmsis.h" /* For CPU related defintiions */ +#include "glcd_mps3.h" /* LCD functions. */ + +/** Platform definitions. TODO: These should be removed. */ +#include "peripheral_memmap.h" /* Peripheral memory map definitions. */ +#include "peripheral_irqs.h" /* IRQ numbers for this platform. */ + +/** + * @brief Initialises the platform components. + * @return 0 if successful, error code otherwise. + */ +int platform_init(void); + +/** + * @brief Teardown for platform components. + */ +void platform_release(void); + +/** + * @brief Sets the platform name. + * @param[out] name Name of the platform to be set + * @param[in] size Size of the input buffer + */ +void platform_name(char* name, size_t size); -#endif /* PLATFORM_DRIVER_H */ +#endif /* PLATFORM_DRIVERS_H */ diff --git a/source/hal/platform/mps3/include/smm_mps3.h b/source/hal/platform/mps3/include/smm_mps3.h deleted file mode 100644 index 1c0e0f2..0000000 --- a/source/hal/platform/mps3/include/smm_mps3.h +++ /dev/null @@ -1,615 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef SMM_MPS3_H -#define SMM_MPS3_H - -#include "cmsis.h" /* Device specific header file. */ -#include "peripheral_memmap.h" /* Peripheral memory map definitions. */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/******************************************************************************/ -/* FPGA System Register declaration */ -/******************************************************************************/ - -typedef struct -{ - __IO uint32_t LED; /* Offset: 0x000 (R/W) LED connections - * [31:2] : Reserved - * [1:0] : LEDs - */ - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons - * [31:2] : Reserved - * [1:0] : Buttons - */ - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */ - __IO uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */ - __IO uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter - * Increments when 32-bit prescale counter reach zero - */ - __IO uint32_t PRESCALE; /* Offset: 0x01C (R/W) Prescaler - * Bit[31:0] : reload value for prescale counter - */ - __IO uint32_t PSCNTR; /* Offset: 0x020 (R/W) 32-bit Prescale counter - * current value of the pre-scaler counter - * The Cycle Up Counter increment when the prescale down counter reach 0 - * The pre-scaler counter is reloaded with PRESCALE after reaching 0. - */ - uint32_t RESERVED3[1]; - __IO uint32_t SWITCHES; /* Offset: 0x028 (R/W) Switches - * [31:8] : Reserved - * [7:0] : Switches - */ - uint32_t RESERVED4[8]; - __IO uint32_t MISC; /* Offset: 0x04C (R/W) Misc control - * [31:10] : Reserved - * [9] : - * [8] : - * [7] : ADC_SPI_nCS - * [6] : CLCD_BL_CTRL - * [5] : CLCD_RD - * [4] : CLCD_RS - * [3] : CLCD_RESET - * [2] : SHIELD_1_SPI_nCS - * [1] : SHIELD_0_SPI_nCS - * [0] : CLCD_CS - */ -} MPS3_FPGAIO_TypeDef; - -/* MISC register bit definitions. */ - -#define CLCD_CS_Pos 0 -#define CLCD_CS_Msk (1UL< CONTROL - * TX Enable - * <0=> TX disabled - * <1=> TX enabled - * TX IRQ Enable - * <0=> TX IRQ disabled - * <1=> TX IRQ enabled - * RX Enable - * <0=> RX disabled - * <1=> RX enabled - * RX IRQ Enable - * <0=> RX IRQ disabled - * <1=> RX IRQ enabled - * TX Buffer Water Level - * <0=> / IRQ triggers when any space available - * <1=> / IRQ triggers when more than 1 space available - * <2=> / IRQ triggers when more than 2 space available - * <3=> / IRQ triggers when more than 3 space available - * <4=> Undefined! - * <5=> Undefined! - * <6=> Undefined! - * <7=> Undefined! - * RX Buffer Water Level - * <0=> Undefined! - * <1=> / IRQ triggers when less than 1 space available - * <2=> / IRQ triggers when less than 2 space available - * <3=> / IRQ triggers when less than 3 space available - * <4=> / IRQ triggers when less than 4 space available - * <5=> Undefined! - * <6=> Undefined! - * <7=> Undefined! - * FIFO reset - * <0=> Normal operation - * <1=> FIFO reset - * Audio Codec reset - * <0=> Normal operation - * <1=> Assert audio Codec reset - */ - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; /* STATUS - * TX Buffer alert - * <0=> TX buffer don't need service yet - * <1=> TX buffer need service - * RX Buffer alert - * <0=> RX buffer don't need service yet - * <1=> RX buffer need service - * TX Buffer Empty - * <0=> TX buffer have data - * <1=> TX buffer empty - * TX Buffer Full - * <0=> TX buffer not full - * <1=> TX buffer full - * RX Buffer Empty - * <0=> RX buffer have data - * <1=> RX buffer empty - * RX Buffer Full - * <0=> RX buffer not full - * <1=> RX buffer full - */ - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; /* ERROR - * TX error - * <0=> Okay - * <1=> TX overrun/underrun - * RX error - * <0=> Okay - * <1=> RX overrun/underrun - */ - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; /* ERRORCLR - * TX error - * <0=> Okay - * <1=> Clear TX error - * RX error - * <0=> Okay - * <1=> Clear RX error - */ - }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; /* Divide ratio for Left/Right clock - * TX error (default 0x80) - */ - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; /* Transmit buffer - * Right channel - * Left channel - */ - - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; /* Receive buffer - * Right channel - * Left channel - */ - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; /* Integration Test Control Register - * ITEN - * <0=> Normal operation - * <1=> Integration Test mode enable - */ - __O uint32_t ITIP1; /* Integration Test Input Register 1 - * SDIN - */ - __O uint32_t ITOP1; /* Integration Test Output Register 1 - * SDOUT - * SCLK - * LRCK - * IRQOUT - */ -} MPS3_I2S_TypeDef; - -#define I2S_CONTROL_TXEN_Pos 0 -#define I2S_CONTROL_TXEN_Msk (1UL< -#include /* Container for timestamp up-counters. */ typedef struct _mps3_time_counter { @@ -47,7 +46,7 @@ base_time_counter get_time_counter(void); * @brief Gets the duration elapsed between two counters in milliseconds. * @param[in] start Pointer to base_time_counter value at start time. * @param[in] end Pointer to base_time_counter value at end. - * @returns Difference in milliseconds between the two give counters + * @returns Difference in milliseconds between the two give counters * expressed as an unsigned integer. **/ uint32_t get_duration_milliseconds(base_time_counter *start, @@ -57,7 +56,7 @@ uint32_t get_duration_milliseconds(base_time_counter *start, * @brief Gets the duration elapsed between two counters in microseconds. * @param[in] start Pointer to base_time_counter value at start time. * @param[in] end Pointer to base_time_counter value at end. - * @returns Difference in microseconds between the two give counters + * @returns Difference in microseconds between the two give counters * expressed as an unsigned integer. **/ uint32_t get_duration_microseconds(base_time_counter *start, @@ -83,4 +82,9 @@ void start_cycle_counter(void); **/ void stop_cycle_counter(void); +/** + * @brief System tick interrupt handler. + **/ +void SysTick_Handler(void); + #endif /* TIMER_MPS3_H */ diff --git a/source/hal/platform/mps3/source/device_mps3.c b/source/hal/platform/mps3/source/device_mps3.c index fa57c2e..de715fb 100644 --- a/source/hal/platform/mps3/source/device_mps3.c +++ b/source/hal/platform/mps3/source/device_mps3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,11 +21,9 @@ #include -extern uint32_t GetSystemCoreClock(void); - uint32_t GetMPS3CoreClock(void) { - const uint32_t default_clock = GetSystemCoreClock(); + const uint32_t default_clock = 32000000 /* 32 MHz clock */; static int warned_once = 0; if (0 != MPS3_SCC->CFG_ACLK) { if (default_clock != MPS3_SCC->CFG_ACLK) { diff --git a/source/hal/platform/mps3/source/include/device_mps3.h b/source/hal/platform/mps3/source/include/device_mps3.h new file mode 100644 index 0000000..445965d --- /dev/null +++ b/source/hal/platform/mps3/source/include/device_mps3.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef DEVICE_MPS3_H +#define DEVICE_MPS3_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "smm_mps3.h" /* Memory map for MPS3. */ + +#include + +#define PERIF_CLK (25000000) /* Clock source for APB peripherals */ + +typedef struct _CMSDK_UART_TypeDef_ +{ + __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register. */ + __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register. */ + __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register. */ + + union { + __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register. */ + __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register. */ + }; + __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register. */ + +} CMSDK_UART_TypeDef; + +#define CMSDK_UART0 ((CMSDK_UART_TypeDef *)CMSDK_UART0_BASE) + +/* CMSDK_UART DATA Register Definitions. */ +#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position. */ +#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask. */ + +/* CMSDK_UART STATE Register Definitions. */ +#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position. */ +#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask. */ + +#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position. */ +#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask. */ + +#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position. */ +#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask. */ + +#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position. */ +#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask. */ + +/* CMSDK_UART CTRL Register Definitions. */ +#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position. */ +#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask. */ + +#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position. */ +#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask. */ + +#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position. */ +#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask. */ + +#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position. */ +#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask. */ + +#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position. */ +#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask. */ + +#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position. */ +#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask. */ + +#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position. */ +#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask. */ + +/* CMSDK_UART INTSTATUS\INTCLEAR Register Definitions. */ +#define CMSDK_UART_INT_RXORIRQ_Pos 3 /* CMSDK_UART INT: RXORIRQ Position. */ +#define CMSDK_UART_INT_RXORIRQ_Msk (0x01ul << CMSDK_UART_INT_RXORIRQ_Pos) /* CMSDK_UART INT: RXORIRQ Mask. */ + +#define CMSDK_UART_INT_TXORIRQ_Pos 2 /* CMSDK_UART INT: TXORIRQ Position. */ +#define CMSDK_UART_INT_TXORIRQ_Msk (0x01ul << CMSDK_UART_INT_TXORIRQ_Pos) /* CMSDK_UART INT: TXORIRQ Mask. */ + +#define CMSDK_UART_INT_RXIRQ_Pos 1 /* CMSDK_UART INT: RXIRQ Position. */ +#define CMSDK_UART_INT_RXIRQ_Msk (0x01ul << CMSDK_UART_INT_RXIRQ_Pos) /* CMSDK_UART INT: RXIRQ Mask. */ + +#define CMSDK_UART_INT_TXIRQ_Pos 0 /* CMSDK_UART INT: TXIRQ Position. */ +#define CMSDK_UART_INT_TXIRQ_Msk (0x01ul << CMSDK_UART_INT_TXIRQ_Pos) /* CMSDK_UART INT: TXIRQ Mask. */ + +/* CMSDK_UART BAUDDIV Register Definitions. */ +#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position. */ +#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) + +/** + * @brief Gets the core clock set for MPS3. + * @return Clock value in Hz. + **/ +uint32_t GetMPS3CoreClock(void); + +#ifdef __cplusplus +} +#endif + +#endif /* DEVICE_MPS3_H */ diff --git a/source/hal/platform/mps3/source/include/smm_mps3.h b/source/hal/platform/mps3/source/include/smm_mps3.h new file mode 100644 index 0000000..5a2bcc5 --- /dev/null +++ b/source/hal/platform/mps3/source/include/smm_mps3.h @@ -0,0 +1,616 @@ +/* + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef SMM_MPS3_H +#define SMM_MPS3_H + +#include "cmsis.h" /* For CPU related defintiions */ +#include "peripheral_memmap.h" /* Peripheral memory map definitions. */ + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* FPGA System Register declaration */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t LED; /* Offset: 0x000 (R/W) LED connections + * [31:2] : Reserved + * [1:0] : LEDs + */ + uint32_t RESERVED1[1]; + __IO uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons + * [31:2] : Reserved + * [1:0] : Buttons + */ + uint32_t RESERVED2[1]; + __IO uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */ + __IO uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */ + __IO uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter + * Increments when 32-bit prescale counter reach zero + */ + __IO uint32_t PRESCALE; /* Offset: 0x01C (R/W) Prescaler + * Bit[31:0] : reload value for prescale counter + */ + __IO uint32_t PSCNTR; /* Offset: 0x020 (R/W) 32-bit Prescale counter + * current value of the pre-scaler counter + * The Cycle Up Counter increment when the prescale down counter reach 0 + * The pre-scaler counter is reloaded with PRESCALE after reaching 0. + */ + uint32_t RESERVED3[1]; + __IO uint32_t SWITCHES; /* Offset: 0x028 (R/W) Switches + * [31:8] : Reserved + * [7:0] : Switches + */ + uint32_t RESERVED4[8]; + __IO uint32_t MISC; /* Offset: 0x04C (R/W) Misc control + * [31:10] : Reserved + * [9] : + * [8] : + * [7] : ADC_SPI_nCS + * [6] : CLCD_BL_CTRL + * [5] : CLCD_RD + * [4] : CLCD_RS + * [3] : CLCD_RESET + * [2] : SHIELD_1_SPI_nCS + * [1] : SHIELD_0_SPI_nCS + * [0] : CLCD_CS + */ +} MPS3_FPGAIO_TypeDef; + +/* MISC register bit definitions. */ + +#define CLCD_CS_Pos 0 +#define CLCD_CS_Msk (1UL< CONTROL + * TX Enable + * <0=> TX disabled + * <1=> TX enabled + * TX IRQ Enable + * <0=> TX IRQ disabled + * <1=> TX IRQ enabled + * RX Enable + * <0=> RX disabled + * <1=> RX enabled + * RX IRQ Enable + * <0=> RX IRQ disabled + * <1=> RX IRQ enabled + * TX Buffer Water Level + * <0=> / IRQ triggers when any space available + * <1=> / IRQ triggers when more than 1 space available + * <2=> / IRQ triggers when more than 2 space available + * <3=> / IRQ triggers when more than 3 space available + * <4=> Undefined! + * <5=> Undefined! + * <6=> Undefined! + * <7=> Undefined! + * RX Buffer Water Level + * <0=> Undefined! + * <1=> / IRQ triggers when less than 1 space available + * <2=> / IRQ triggers when less than 2 space available + * <3=> / IRQ triggers when less than 3 space available + * <4=> / IRQ triggers when less than 4 space available + * <5=> Undefined! + * <6=> Undefined! + * <7=> Undefined! + * FIFO reset + * <0=> Normal operation + * <1=> FIFO reset + * Audio Codec reset + * <0=> Normal operation + * <1=> Assert audio Codec reset + */ + /*!< Offset: 0x004 STATUS Register (R/ ) */ + __I uint32_t STATUS; /* STATUS + * TX Buffer alert + * <0=> TX buffer don't need service yet + * <1=> TX buffer need service + * RX Buffer alert + * <0=> RX buffer don't need service yet + * <1=> RX buffer need service + * TX Buffer Empty + * <0=> TX buffer have data + * <1=> TX buffer empty + * TX Buffer Full + * <0=> TX buffer not full + * <1=> TX buffer full + * RX Buffer Empty + * <0=> RX buffer have data + * <1=> RX buffer empty + * RX Buffer Full + * <0=> RX buffer not full + * <1=> RX buffer full + */ + union { + /*!< Offset: 0x008 Error Status Register (R/ ) */ + __I uint32_t ERROR; /* ERROR + * TX error + * <0=> Okay + * <1=> TX overrun/underrun + * RX error + * <0=> Okay + * <1=> RX overrun/underrun + */ + /*!< Offset: 0x008 Error Clear Register ( /W) */ + __O uint32_t ERRORCLR; /* ERRORCLR + * TX error + * <0=> Okay + * <1=> Clear TX error + * RX error + * <0=> Okay + * <1=> Clear RX error + */ + }; + /*!< Offset: 0x00C Divide ratio Register (R/W) */ + __IO uint32_t DIVIDE; /* Divide ratio for Left/Right clock + * TX error (default 0x80) + */ + /*!< Offset: 0x010 Transmit Buffer ( /W) */ + __O uint32_t TXBUF; /* Transmit buffer + * Right channel + * Left channel + */ + + /*!< Offset: 0x014 Receive Buffer (R/ ) */ + __I uint32_t RXBUF; /* Receive buffer + * Right channel + * Left channel + */ + uint32_t RESERVED1[186]; + __IO uint32_t ITCR; /* Integration Test Control Register + * ITEN + * <0=> Normal operation + * <1=> Integration Test mode enable + */ + __O uint32_t ITIP1; /* Integration Test Input Register 1 + * SDIN + */ + __O uint32_t ITOP1; /* Integration Test Output Register 1 + * SDOUT + * SCLK + * LRCK + * IRQOUT + */ +} MPS3_I2S_TypeDef; + +#define I2S_CONTROL_TXEN_Pos 0 +#define I2S_CONTROL_TXEN_Msk (1UL< /* For strncpy */ + +/** + * @brief Checks if the platform is valid by checking + * the CPU ID for the FPGA implementation against + * the register from the CPU core. + * @return 0 if successful, 1 otherwise + */ +static int verify_platform(void); + +int platform_init(void) +{ + int err = 0; + + SystemCoreClockUpdate(); /* From start up code */ + + /* UART init - will enable valid use of printf (stdout + * re-directed at this UART (UART0) */ + UartStdOutInit(); + + if (0 != (err = verify_platform())) { + return err; + } + + /** TODO: Add ARM NPU and TA init here */ + return 0; +} + +void platform_release(void) +{ + __disable_irq(); +} + +void platform_name(char* name, size_t size) +{ + strncpy(name, DESIGN_NAME, size); +} + +#define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb)) +#define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb)) +#define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb)) + +static int verify_platform(void) +{ + uint32_t id = 0; + uint32_t fpgaid = 0; + uint32_t apnote = 0; + uint32_t rev = 0; + uint32_t aid = 0; + uint32_t fpga_clk = 0; + const uint32_t ascii_A = (uint32_t)('A'); + + /* Initialise the LEDs as the switches are */ + MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF; + + info("Processor internal clock: %" PRIu32 "Hz\n", GetMPS3CoreClock()); + + /* Get revision information from various registers */ + rev = MPS3_SCC->CFG_REG4; + fpgaid = MPS3_SCC->SCC_ID; + aid = MPS3_SCC->SCC_AID; + apnote = EXTRACT_BITS(fpgaid, 15, 4); + fpga_clk = GetMPS3CoreClock(); + + info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A)); + info("Application Note AN%" PRIx32 ", Revision %c\n", apnote, + (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A)); + info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24)); + info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk); + + /* Display CPU ID */ + id = SCB->CPUID; + info("CPU ID: 0x%08" PRIx32 "\n", id); + + if(EXTRACT_BITS(id, 15, 8) == 0xD2) { + if (EXTRACT_BITS(id, 7, 4) == 2) { + info ("CPU: Cortex-M55 r%dp%d\n\n", + EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); +#if defined (CPU_CORTEX_M55) + /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */ + return 0; +#endif /* CPU_CORTEX_M55 */ + } else if (EXTRACT_BITS(id, 7, 4) == 1) { + info ("CPU: Cortex-M33 r%dp%d\n\n", + EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); +#if defined (CPU_CORTEX_M33) + return 0; +#endif /* CPU_CORTEX_M33 */ + } else if (EXTRACT_BITS(id, 7, 4) == 0) { + info ("CPU: Cortex-M23 r%dp%d\n\n", + EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); + } else { + info ("CPU: Cortex-M processor family"); + } + } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) { + info ("CPU: Cortex-M%d+ r%dp%d\n\n", + EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), + EXTRACT_BITS(id, 3, 0)); + } else { + info ("CPU: Cortex-M%d r%dp%d\n\n", + EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), + EXTRACT_BITS(id, 3, 0)); + } + + /* If the CPU is anything other than M33 or M55, we return 1 */ + printf_err("CPU mismatch!\n"); + return 1; +} diff --git a/source/hal/platform/mps3/source/timer_mps3.c b/source/hal/platform/mps3/source/timer_mps3.c index 9b8914c..16ff4cd 100644 --- a/source/hal/platform/mps3/source/timer_mps3.c +++ b/source/hal/platform/mps3/source/timer_mps3.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,7 +19,18 @@ #include "log_macros.h" #include "device_mps3.h" -#include +static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */ + +/** + * @brief Gets the system tick triggered cycle counter for the CPU. + * @return 64-bit counter value. + **/ +static uint64_t Get_SysTick_Cycle_Count(void); + +/** + * SysTick initialisation + */ +static int Init_SysTick(void); void timer_reset(void) { @@ -111,3 +122,52 @@ void stop_cycle_counter(void) { /* Nothing to do for FPGA */ } + +void SysTick_Handler(void) +{ + /* Increment the cycle counter based on load value. */ + cpu_cycle_count += SysTick->LOAD + 1; +} + +/** + * Gets the current SysTick derived counter value + */ +static uint64_t Get_SysTick_Cycle_Count(void) +{ + uint32_t systick_val; + + NVIC_DisableIRQ(SysTick_IRQn); + systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk; + NVIC_EnableIRQ(SysTick_IRQn); + + return cpu_cycle_count + (SysTick->LOAD - systick_val); +} + +/** + * SysTick initialisation + */ +static int Init_SysTick(void) +{ + const uint32_t ticks_10ms = GetMPS3CoreClock()/100 + 1; + int err = 0; + + /* Reset CPU cycle count value. */ + cpu_cycle_count = 0; + + /* Changing configuration for sys tick => guard from being + * interrupted. */ + NVIC_DisableIRQ(SysTick_IRQn); + + /* SysTick init - this will enable interrupt too. */ + err = SysTick_Config(ticks_10ms); + + /* Enable interrupt again. */ + NVIC_EnableIRQ(SysTick_IRQn); + + /* Wait for SysTick to kick off */ + while (!err && !SysTick->VAL) { + __NOP(); + } + + return err; +} diff --git a/source/hal/platform/native/CMakeLists.txt b/source/hal/platform/native/CMakeLists.txt new file mode 100644 index 0000000..0435cf1 --- /dev/null +++ b/source/hal/platform/native/CMakeLists.txt @@ -0,0 +1,56 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2022 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +######################################################### +# Native target platform support library # +######################################################### + +cmake_minimum_required(VERSION 3.15.6) + +set(PLATFORM_DRIVERS_TARGET platform-drivers) + +project(${PLATFORM_DRIVERS_TARGET} + DESCRIPTION "Platform drivers library for native target" + LANGUAGES C CXX) + +# We should not be cross-compiling +if (${CMAKE_CROSSCOMPILING}) + message(FATAL_ERROR "Native drivers not available when cross-compiling.") +endif() + + +# Create static library +add_library(${PLATFORM_DRIVERS_TARGET} STATIC) + +## Include directories - public +target_include_directories(${PLATFORM_DRIVERS_TARGET} + PUBLIC + include) + +## Platform sources +target_sources(${PLATFORM_DRIVERS_TARGET} + PRIVATE + source/platform_drivers.c) + +# Add dependencies: +target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC log) + +# Display status: +message(STATUS "*******************************************************") +message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET}) +message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR}) +message(STATUS "*******************************************************") diff --git a/source/hal/platform/native/include/platform_drivers.h b/source/hal/platform/native/include/platform_drivers.h new file mode 100644 index 0000000..ca6b6e0 --- /dev/null +++ b/source/hal/platform/native/include/platform_drivers.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PLATFORM_DRIVERS_H +#define PLATFORM_DRIVERS_H + +#include "log_macros.h" /* Logging related helpers. */ + +/** + * @brief Initialises the platform components. + * @return 0 if successful, error code otherwise. + */ +int platform_init(void); + +/** + * @brief Teardown for platform components. + */ +void platform_release(void); + +/** + * @brief Sets the platform name. + * @param[out] name Name of the platform to be set + * @param[in] size Size of the input buffer + */ +void platform_name(char* name, size_t size); + +#endif /* PLATFORM_DRIVERS_H */ diff --git a/source/hal/platform/native/source/platform_drivers.c b/source/hal/platform/native/source/platform_drivers.c new file mode 100644 index 0000000..10db99a --- /dev/null +++ b/source/hal/platform/native/source/platform_drivers.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "platform_drivers.h" + +#include + +int platform_init(void) +{ + return 0; +} + +void platform_release(void) +{} + +void platform_name(char* name, size_t size) +{ + strncpy(name, "native", size); +} \ No newline at end of file diff --git a/source/hal/platform/simple/CMakeLists.txt b/source/hal/platform/simple/CMakeLists.txt index cd3a2bc..44c4089 100644 --- a/source/hal/platform/simple/CMakeLists.txt +++ b/source/hal/platform/simple/CMakeLists.txt @@ -72,7 +72,8 @@ target_include_directories(${PLATFORM_DRIVERS_TARGET} target_sources(${PLATFORM_DRIVERS_TARGET} PRIVATE source/stubs_glcd.c - source/timer_simple_platform.c) + source/timer_simple_platform.c + source/platform_drivers.c) ## Platform component: uart target_sources(${PLATFORM_DRIVERS_TARGET} diff --git a/source/hal/platform/simple/include/platform_drivers.h b/source/hal/platform/simple/include/platform_drivers.h index 0fb092e..c9928c0 100644 --- a/source/hal/platform/simple/include/platform_drivers.h +++ b/source/hal/platform/simple/include/platform_drivers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,18 +15,36 @@ * limitations under the License. */ -#ifndef PLATFORM_DRIVER_H -#define PLATFORM_DRIVER_H +#ifndef PLATFORM_DRIVERS_H +#define PLATFORM_DRIVERS_H #include "log_macros.h" /* Logging related helpers. */ /* Platform components */ -#include "uart_stdout.h" /* stdout over UART. */ -#include "stubs/glcd.h" /* LCD stubs to support use cases that use LCD */ +#include "stubs/glcd.h" /* LCD stubs to support use cases that use LCD */ #include "timer_simple_platform.h" /* timer implementation */ +#include "cmsis.h" /* For CPU related defintiions */ -#include "cmsis.h" /* CPU device specific header file */ -#include "peripheral_memmap.h" /* peripheral memory map definitions */ -#include "peripheral_irqs.h" /* IRQ numbers for the platform */ +/** Platform definitions. TODO: These should be removed. */ +#include "peripheral_memmap.h" /* Peripheral memory map definitions. */ +#include "peripheral_irqs.h" /* IRQ numbers for this platform. */ -#endif /* PLATFORM_DRIVER_H */ +/** + * @brief Initialises the platform components. + * @return 0 if successful, error code otherwise. + */ +int platform_init(void); + +/** + * @brief Teardown for platform components. + */ +void platform_release(void); + +/** + * @brief Sets the platform name. + * @param[out] name Name of the platform to be set + * @param[in] size Size of the input buffer + */ +void platform_name(char* name, size_t size); + +#endif /* PLATFORM_DRIVERS_H */ diff --git a/source/hal/platform/simple/include/stubs/glcd.h b/source/hal/platform/simple/include/stubs/glcd.h index 5915f7d..b31938f 100644 --- a/source/hal/platform/simple/include/stubs/glcd.h +++ b/source/hal/platform/simple/include/stubs/glcd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,6 +17,8 @@ #ifndef STUBS_SIMPLE_PLATFORM_H #define STUBS_SIMPLE_PLATFORM_H +#include + /****************************************************************************/ /* Definitions and stub functions for modules currently */ /* unavailable on this target platform */ @@ -58,10 +60,10 @@ void GLCD_Bitmap(unsigned int x, unsigned int y, * @param[in] downsample_factor factor by which the image * is downsampled by. */ -void GLCD_Image(void *data, const unsigned int width, - const unsigned int height, const unsigned int channels, - const unsigned int pos_x, const unsigned int pos_y, - const unsigned int downsample_factor); +void GLCD_Image(const void *data, const uint32_t width, + const uint32_t height, const uint32_t channels, + const uint32_t pos_x, const uint32_t pos_y, + const uint32_t downsample_factor); /** * @brief Clear display diff --git a/source/hal/platform/simple/include/timer_simple_platform.h b/source/hal/platform/simple/include/timer_simple_platform.h index 03d8245..4df22da 100644 --- a/source/hal/platform/simple/include/timer_simple_platform.h +++ b/source/hal/platform/simple/include/timer_simple_platform.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -51,4 +51,9 @@ void start_cycle_counter(void); */ void stop_cycle_counter(void); +/** + * @brief System tick interrupt handler. + **/ +void SysTick_Handler(void); + #endif /* TIMER_SIMPLE_PLATFORM_H */ diff --git a/source/hal/platform/simple/source/platform_drivers.c b/source/hal/platform/simple/source/platform_drivers.c new file mode 100644 index 0000000..c92a964 --- /dev/null +++ b/source/hal/platform/simple/source/platform_drivers.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "platform_drivers.h" + +#include "uart_stdout.h" +#include + +int platform_init(void) +{ + SystemCoreClockUpdate(); /* From start up code */ + + /* UART init - will enable valid use of printf (stdout + * re-directed at this UART (UART0) */ + UartStdOutInit(); + + info("%s: complete\n", __FUNCTION__); + + /** TODO: Add ARM NPU and TA init here */ + return 0; +} + +void platform_release(void) +{ + __disable_irq(); +} + +void platform_name(char* name, size_t size) +{ + strncpy(name, DESIGN_NAME, size); +} diff --git a/source/hal/platform/simple/source/stubs_glcd.c b/source/hal/platform/simple/source/stubs_glcd.c index 6b60dcd..d843cf4 100644 --- a/source/hal/platform/simple/source/stubs_glcd.c +++ b/source/hal/platform/simple/source/stubs_glcd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,9 +31,10 @@ void GLCD_Bitmap(unsigned int x, unsigned int y, UNUSED(bitmap); } -void GLCD_Image(void *data, const unsigned int width, const unsigned int height, - const unsigned int channels, const unsigned int pos_x, - const unsigned int pos_y, const unsigned int downsample_factor) +void GLCD_Image(const void *data, const uint32_t width, + const uint32_t height, const uint32_t channels, + const uint32_t pos_x, const uint32_t pos_y, + const uint32_t downsample_factor) { UNUSED(data); UNUSED(pos_x); diff --git a/source/hal/platform/simple/source/timer_simple_platform.c b/source/hal/platform/simple/source/timer_simple_platform.c index 4bcd07b..3d28261 100644 --- a/source/hal/platform/simple/source/timer_simple_platform.c +++ b/source/hal/platform/simple/source/timer_simple_platform.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,11 +16,26 @@ */ #include "timer_simple_platform.h" -#include "irqs.h" -#include "log_macros.h" +#include "log_macros.h" /* Logging macros */ +#include "cmsis.h" /* For CPU related defintiions */ #include +static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */ +extern uint32_t SystemCoreClock; /* Expected to come from the cmsis-device lib */ + +/** + * @brief Gets the system tick triggered cycle counter for the CPU. + * @return 64-bit counter value. + **/ +static uint64_t Get_SysTick_Cycle_Count(void); + +/** + * SysTick initialisation + */ +static int Init_SysTick(void); + + base_time_counter get_time_counter(void) { base_time_counter t = { @@ -56,3 +71,53 @@ void stop_cycle_counter(void) { /* Add any custom requirement for this platform here */ } + + +void SysTick_Handler(void) +{ + /* Increment the cycle counter based on load value. */ + cpu_cycle_count += SysTick->LOAD + 1; +} + +/** + * Gets the current SysTick derived counter value + */ +static uint64_t Get_SysTick_Cycle_Count(void) +{ + uint32_t systick_val; + + NVIC_DisableIRQ(SysTick_IRQn); + systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk; + NVIC_EnableIRQ(SysTick_IRQn); + + return cpu_cycle_count + (SysTick->LOAD - systick_val); +} + +/** + * SysTick initialisation + */ +static int Init_SysTick(void) +{ + const uint32_t ticks_10ms = SystemCoreClock/100 + 1; + int err = 0; + + /* Reset CPU cycle count value. */ + cpu_cycle_count = 0; + + /* Changing configuration for sys tick => guard from being + * interrupted. */ + NVIC_DisableIRQ(SysTick_IRQn); + + /* SysTick init - this will enable interrupt too. */ + err = SysTick_Config(ticks_10ms); + + /* Enable interrupt again. */ + NVIC_EnableIRQ(SysTick_IRQn); + + /* Wait for SysTick to kick off */ + while (!err && !SysTick->VAL) { + __NOP(); + } + + return err; +} \ No newline at end of file diff --git a/source/hal/profiles/bare-metal/data_acquisition/data_acq.c b/source/hal/profiles/bare-metal/data_acquisition/data_acq.c index 1e40b02..7113a24 100644 --- a/source/hal/profiles/bare-metal/data_acquisition/data_acq.c +++ b/source/hal/profiles/bare-metal/data_acquisition/data_acq.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,6 +17,8 @@ #include "data_acq.h" #include "bsp.h" +#include "log_macros.h" +#include "uart_stdout.h" #include #include @@ -31,7 +33,6 @@ static int get_uart_user_input(char* user_input, int size) { if (true != GetLine(user_input, size - 1)) { - printf_err("invalid input\n"); return 1; } return 0; diff --git a/source/hal/profiles/bare-metal/data_presentation/lcd/lcd_img.c b/source/hal/profiles/bare-metal/data_presentation/lcd/lcd_img.c index 7064396..bb950c3 100644 --- a/source/hal/profiles/bare-metal/data_presentation/lcd/lcd_img.c +++ b/source/hal/profiles/bare-metal/data_presentation/lcd/lcd_img.c @@ -17,6 +17,7 @@ #include "lcd_img.h" #include "bsp.h" +#include "log_macros.h" #include #include diff --git a/source/hal/profiles/bare-metal/timer/platform_timer.c b/source/hal/profiles/bare-metal/timer/platform_timer.c index c8e7252..11ccf8b 100644 --- a/source/hal/profiles/bare-metal/timer/platform_timer.c +++ b/source/hal/profiles/bare-metal/timer/platform_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. All rights reserved. + * Copyright (c) 2021-2022 Arm Limited. All rights reserved. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,6 +16,7 @@ */ #include "bsp.h" #include "timer.h" +#include "log_macros.h" #include #include diff --git a/source/hal/profiles/bare-metal/utils/include/system_init.h b/source/hal/profiles/bare-metal/utils/include/system_init.h deleted file mode 100644 index 84e0305..0000000 --- a/source/hal/profiles/bare-metal/utils/include/system_init.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef BAREMETAL_SYSTEM_INIT_H -#define BAREMETAL_SYSTEM_INIT_H - -#include "bsp.h" - -/** - * @brief Initialises the platform (MPS3 FPGA board or Fixed Virtual Platform) - * Updates the system core clock and initialises the UART. It also - * verifies that the Cortex-M CPU variant being used matches the expected - * value if running on MPS3. - * @return 0 if successful, error code otherwise. -*/ -int system_init(void); - -/** - * @brief Releases the platform (MPS3 FPGA board or Fixed Virtual Platform). - **/ -void system_release(void); - -/** - * @brief Return the name the platform (MPS3 FPGA board or Fixed Virtual Platform). - * @param[out] name Platform name string. - * @param[in] size Name string length. - **/ -void system_name(char* name, size_t size); - -#endif /* BAREMETAL_SYSTEM_INIT_H */ diff --git a/source/hal/profiles/bare-metal/utils/system_init.c b/source/hal/profiles/bare-metal/utils/system_init.c deleted file mode 100644 index 23af14f..0000000 --- a/source/hal/profiles/bare-metal/utils/system_init.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "system_init.h" - -#include -#include - -#if defined(MPS3_PLATFORM) -#define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb)) -#define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb)) -#define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb)) -#endif /* MPS3_PLATFORM */ - -int system_init(void) -{ -#if defined(MPS3_PLATFORM) - uint32_t id = 0; - uint32_t fpgaid = 0; - uint32_t apnote = 0; - uint32_t rev = 0; - uint32_t aid = 0; - uint32_t fpga_clk = 0; - const uint32_t ascii_A = (uint32_t)('A'); - - /* Initialise the LEDs as the switches are */ - MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF; -#endif - - /* UART init - will enable valid use of printf (stdout - * re-directed at this UART (UART0) */ - UartStdOutInit(); - info("Processor internal clock: %" PRIu32 "Hz\n", GetSystemCoreClock()); - -#if defined(MPS3_PLATFORM) - /* Get revision information from various registers */ - rev = MPS3_SCC->CFG_REG4; - fpgaid = MPS3_SCC->SCC_ID; - aid = MPS3_SCC->SCC_AID; - apnote = EXTRACT_BITS(fpgaid, 15, 4); - fpga_clk = GetMPS3CoreClock(); - - info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A)); - info("Application Note AN%" PRIx32 ", Revision %c\n", apnote, - (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A)); - info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24)); - info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk); - - /* Display CPU ID */ - id = SCB->CPUID; - info("CPU ID: 0x%08" PRIx32 "\n", id); - - if(EXTRACT_BITS(id, 15, 8) == 0xD2) { - if (EXTRACT_BITS(id, 7, 4) == 2) { - info ("CPU: Cortex-M55 r%dp%d\n\n", - EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); -#if defined (CPU_CORTEX_M55) - /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */ - return 0; -#endif /* CPU_CORTEX_M55 */ - } else if (EXTRACT_BITS(id, 7, 4) == 1) { - info ("CPU: Cortex-M33 r%dp%d\n\n", - EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); -#if defined (CPU_CORTEX_M33) - return 0; -#endif /* CPU_CORTEX_M33 */ - } else if (EXTRACT_BITS(id, 7, 4) == 0) { - info ("CPU: Cortex-M23 r%dp%d\n\n", - EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); - } else { - info ("CPU: Cortex-M processor family"); - } - } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) { - info ("CPU: Cortex-M%d+ r%dp%d\n\n", - EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), - EXTRACT_BITS(id, 3, 0)); - } else { - info ("CPU: Cortex-M%d r%dp%d\n\n", - EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), - EXTRACT_BITS(id, 3, 0)); - } -#else /* MPS3_PLATFORM */ - - info("%s: complete\n", __FUNCTION__); - return 0; -#endif /* MPS3_PLATFORM */ - - /* If the CPU is anything other than M33 or M55, we return 1 */ - printf_err("CPU mismatch!\n"); - return 1; -} - -void system_release(void) -{ - __disable_irq(); -} - -void system_name(char* name, size_t size) -{ - strncpy(name, DESIGN_NAME, size); -} \ No newline at end of file diff --git a/source/hal/profiles/native/utils/include/system_init.h b/source/hal/profiles/native/utils/include/system_init.h deleted file mode 100644 index 5d3fcd0..0000000 --- a/source/hal/profiles/native/utils/include/system_init.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef NATIVE_SYSTEM_INIT_H -#define NATIVE_SYSTEM_INIT_H - -#include -/** - * @brief Platform initialisation for native platform. - **/ -int system_init(void); - -/** - * @brief Platform release for native platform. - **/ -void system_release(void); - -/** - * @brief Returns the name of the platform. - * @param[out] name Platform name string. - * @param[in] size Name string length. - */ -void system_name(char* name, size_t size); - -#endif /* NATIVE_SYSTEM_INIT_H */ diff --git a/source/hal/profiles/native/utils/system_init.c b/source/hal/profiles/native/utils/system_init.c deleted file mode 100644 index 8e0b768..0000000 --- a/source/hal/profiles/native/utils/system_init.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited. All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "system_init.h" - -#include - -int system_init(void) -{ - return 0; -} - -void system_release(void) -{} - -void system_name(char* name, size_t size) -{ - strncpy(name, "native", size); -} \ No newline at end of file diff --git a/source/profiler/CMakeLists.txt b/source/profiler/CMakeLists.txt index e59dc01..b02b276 100644 --- a/source/profiler/CMakeLists.txt +++ b/source/profiler/CMakeLists.txt @@ -31,6 +31,11 @@ target_sources(profiler target_include_directories(profiler PUBLIC include) +# Set the CPU profiling defintiion +if (CPU_PROFILE_ENABLED) + target_compile_definitions(profiler PRIVATE CPU_PROFILE_ENABLED) +endif() + # Profiling API depends on the logging interface and the HAL library. target_link_libraries(profiler PRIVATE log hal) -- cgit v1.2.1