diff options
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/mem_layout')
3 files changed, 322 insertions, 0 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct new file mode 100644 index 0000000..293193e --- /dev/null +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-200.sct @@ -0,0 +1,102 @@ +; Copyright (c) 2021 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; +; Sections used: +;--------------------------------------------------------- +; | Start | End | Size | Remarks | +;-|-------------|-------------|-------------|------------| +; | 0x0000_0000 | 0x0010_0000 | 0x0010_0000 | ITCM (RO) | +; | 0x0010_0000 | 0x0030_0000 | 0x0020_0000 | BRAM (RW) | +; | 0x2000_0000 | 0x2040_0000 | 0x0040_0000 | DTCM (RW) | +; | 0x6000_0000 | 0x6200_0000 | 0x0200_0000 | DRAM (RW) | +;-|-------------|-------------|-------------|------------| +; ITCM is aliased at 0x1000_0000 (single bank) +; BRAM is aliased at 0x1010_0000 +; DTCM is aliased at 0x3000_0000 (four banks of 1MiB each) +; DRAM is aliased at 0x7000_0000 (section is 256MiB) +; +; Note: Ethos-U55 can only access DRAM and BRAM sections +;--------------------------------------------------------- +; First load region +;--------------------------------------------------------- +LOAD_REGION_0 0x00000000 0x00100000 +{ + ;----------------------------------------------------- + ; First part of code mem - 1MiB + ;----------------------------------------------------- + itcm.bin 0x00000000 0x00100000 + { + *.o (RESET, +First) + * (InRoot$$Sections) + .ANY (+RO) + } + + ;----------------------------------------------------- + ; Code memory's 2MiB - reserved for activation buffers + ; Make sure this is uninitialised. + ;----------------------------------------------------- + bram.bin 0x00100000 UNINIT 0x00200000 + { + ; activation buffers a.k.a tensor arena + *.o (.bss.NoInit.activation_buf) + } + + ;----------------------------------------------------- + ; 1MiB bank is used for any other RW or ZI data + ; Note: this region is internal to the Cortex-M CPU + ;----------------------------------------------------- + dtcm.bin 0x20000000 0x00100000 + { + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 128kiB of stack space within SRAM region + ;----------------------------------------------------- + ARM_LIB_STACK 0x20100000 EMPTY ALIGN 8 0x00020000 + {} + + ;----------------------------------------------------- + ; 2MiB of heap space within the SRAM region + ;----------------------------------------------------- + ARM_LIB_HEAP 0x20200000 EMPTY ALIGN 8 0x00200000 + {} +} + +;--------------------------------------------------------- +; Second load region +;--------------------------------------------------------- +LOAD_REGION_1 0x60000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DRAM space for nn model and input vectors + ;----------------------------------------------------- + dram.bin 0x60000000 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model + *.o (nn_model) + + ; if the activation buffer (tensor arena) doesn't + ; fit in the SRAM region, we accommodate it here + *.o (activation_buf) + } +} diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct new file mode 100644 index 0000000..327d511 --- /dev/null +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct @@ -0,0 +1,118 @@ +; Copyright (c) 2021 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping information. +; +; Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and +; the model should only be placed in those regions. +; +;--------------------------------------------------------- +; First load region (ITCM) +;--------------------------------------------------------- +LOAD_REGION_0 0x00000000 0x00080000 +{ + ;----------------------------------------------------- + ; First part of code mem - 512kiB + ;----------------------------------------------------- + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + * (InRoot$$Sections) + + ; Essentially only RO-CODE, RO-DATA is in a + ; different region. + .ANY (+RO) + } + + ;----------------------------------------------------- + ; 128kiB of 512kiB DTCM is used for any other RW or ZI + ; data. Note: this region is internal to the Cortex-M + ; CPU. + ;----------------------------------------------------- + dtcm.bin 0x20000000 0x00020000 + { + ; Any R/W and/or zero initialised data + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 384kiB of stack space within the DTCM region. See + ; `dtcm.bin` for the first section. Note: by virtue of + ; being part of DTCM, this region is only accessible + ; from Cortex-M55. + ;----------------------------------------------------- + ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00060000 + {} + + ;----------------------------------------------------- + ; SSE-300's internal SRAM of 4MiB - reserved for + ; activation buffers. + ; This region should have 3 cycle read latency from + ; both Cortex-M55 and Ethos-U55 + ;----------------------------------------------------- + isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000 + { + ; activation buffers a.k.a tensor arena + *.o (.bss.NoInit.activation_buf) + } +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DRAM space for neural network model, + ; input vectors and labels. If the activation buffer + ; size required by the network is bigger than the + ; SRAM size available, it is accommodated here. + ;----------------------------------------------------- + dram.bin 0x70000000 ALIGN 16 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model + *.o (nn_model) + + ; labels + *.o (labels) + + ; if the activation buffer (tensor arena) doesn't + ; fit in the SRAM region, we accommodate it here + *.o (activation_buf) + } + + ;----------------------------------------------------- + ; First 256kiB of BRAM (FPGA SRAM) used for RO data. + ; Note: Total BRAM size available is 2MiB. + ;----------------------------------------------------- + bram.bin 0x11000000 ALIGN 8 0x00040000 + { + ; RO data (incl. unwinding tables for debugging) + .ANY (+RO-DATA) + } + + ;----------------------------------------------------- + ; Remaining part of the 2MiB BRAM used as heap space. + ; 0x00200000 - 0x00040000 = 0x001C0000 (1.75 MiB) + ;----------------------------------------------------- + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x001C0000 + {} +} diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct new file mode 100644 index 0000000..a1ffb49 --- /dev/null +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct @@ -0,0 +1,102 @@ +; Copyright (c) 2021 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; ************************************************************* +; *** Scatter-Loading Description File *** +; ************************************************************* +; +;--------------------------------------------------------- +; First load region (ITCM) +;--------------------------------------------------------- +LOAD_REGION_0 0x00000000 0x00080000 +{ + ;----------------------------------------------------- + ; First part of code mem - 512kiB + ;----------------------------------------------------- + itcm.bin 0x00000000 0x00080000 + { + *.o (RESET, +First) + * (InRoot$$Sections) + + ; Essentially only RO-CODE, RO-DATA is in a + ; different region. + .ANY (+RO) + } + + ;----------------------------------------------------- + ; BRAM or FPGA data SRAM region worth 2MiB + ;----------------------------------------------------- + bram.bin 0x11000000 UNINIT ALIGN 16 0x00200000 + { + ; activation buffers a.k.a tensor arena + *.o (.bss.NoInit.activation_buf) + } + + ;----------------------------------------------------- + ; 128kiB of 512kiB bank is used for any other RW or ZI + ; data. Note: this region is internal to the Cortex-M + ; CPU + ;----------------------------------------------------- + dtcm.bin 0x20000000 0x00020000 + { + .ANY(+RW +ZI) + } + + ;----------------------------------------------------- + ; 128kiB of stack space within the DTCM region + ;----------------------------------------------------- + ARM_LIB_STACK 0x20020000 EMPTY ALIGN 8 0x00020000 + {} + + ;----------------------------------------------------- + ; 256kiB of heap space within the DTCM region + ;----------------------------------------------------- + ARM_LIB_HEAP 0x20040000 EMPTY ALIGN 8 0x00040000 + {} +} + +;--------------------------------------------------------- +; Second load region (DDR) +;--------------------------------------------------------- +LOAD_REGION_1 0x70000000 0x02000000 +{ + ;----------------------------------------------------- + ; 32 MiB of DRAM space for nn model and input vectors + ;----------------------------------------------------- + dram.bin 0x70000000 ALIGN 16 0x02000000 + { + ; nn model's baked in input matrices + *.o (ifm) + + ; nn model + *.o (nn_model) + + ; if the activation buffer (tensor arena) doesn't + ; fit in the SRAM region, we accommodate it here + *.o (activation_buf) + } + + ;----------------------------------------------------- + ; SSE-300's internal SRAM of 2MiB - reserved for + ; activation buffers. + ; This region should have 3 cycle read latency from + ; both Cortex-M55 and Ethos-U55 + ;----------------------------------------------------- + isram.bin 0x31000000 0x00080000 + { + ; RO data (incl. unwinding tables for debugging) + .ANY (+RO-DATA) + } +} |