diff options
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct')
| -rw-r--r-- | source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct index e84d81e..5825d47 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct @@ -18,8 +18,9 @@ ; ************************************************************* ; Please see docs/sections/appendix.md for memory mapping information. ; -; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and -; the model should only be placed in those regions. +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR +; sections => activation buffers and the model should only +; be placed in those regions. ; ;--------------------------------------------------------- ; First load region (ITCM) @@ -60,17 +61,18 @@ LOAD_REGION_0 0x00000000 0x00080000 {} ;----------------------------------------------------- - ; SSE-300's internal SRAM of 4MiB - reserved for + ; SSE-300's internal SRAM of 2MiB - reserved for ; activation buffers. ; This region should have 3 cycle read latency from ; both Cortex-M55 and Ethos-U NPU ;----------------------------------------------------- - isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000 + isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 { ; Cache area (if used) *.o (.bss.NoInit.ethos_u_cache) - ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram + ; activation buffers a.k.a tensor arena when + ; memory mode sram only or shared sram *.o (.bss.NoInit.activation_buf_sram) } } @@ -103,7 +105,7 @@ LOAD_REGION_1 0x70000000 0x02000000 ;----------------------------------------------------- ; First 256kiB of BRAM (FPGA SRAM) used for RO data. - ; Note: Total BRAM size available is 2MiB. + ; Note: Total BRAM size available is 1MiB. ;----------------------------------------------------- bram.bin 0x11000000 ALIGN 8 0x00040000 { @@ -112,9 +114,9 @@ LOAD_REGION_1 0x70000000 0x02000000 } ;----------------------------------------------------- - ; 960 KiB of remaining part of the 2MiB BRAM used as - ; heap space. 0x000F0000 of 0x0x001C0000 available. + ; 768 KiB of remaining part of the 1MiB BRAM used as + ; heap space. ;----------------------------------------------------- - ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000F0000 + ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 {} } |