diff options
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct')
| -rw-r--r-- | source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct index 0c6a388..e84d81e 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct @@ -16,6 +16,10 @@ ; ************************************************************* ; *** Scatter-Loading Description File *** ; ************************************************************* +; Please see docs/sections/appendix.md for memory mapping information. +; +; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and +; the model should only be placed in those regions. ; ;--------------------------------------------------------- ; First load region (ITCM) @@ -63,8 +67,11 @@ LOAD_REGION_0 0x00000000 0x00080000 ;----------------------------------------------------- isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000 { - ; activation buffers a.k.a tensor arena - *.o (.bss.NoInit.activation_buf) + ; Cache area (if used) + *.o (.bss.NoInit.ethos_u_cache) + + ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram + *.o (.bss.NoInit.activation_buf_sram) } } @@ -84,15 +91,14 @@ LOAD_REGION_1 0x70000000 0x02000000 ; nn model's baked in input matrices *.o (ifm) - ; nn model + ; nn model's default space *.o (nn_model) ; labels *.o (labels) - ; if the activation buffer (tensor arena) doesn't - ; fit in the SRAM region, we accommodate it here - *.o (activation_buf) + ; activation buffers a.k.a tensor arena when memory mode dedicated sram + *.o (activation_buf_dram) } ;----------------------------------------------------- |