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Diffstat (limited to 'scripts/vela/vela.ini')
-rw-r--r-- | scripts/vela/vela.ini | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/scripts/vela/vela.ini b/scripts/vela/vela.ini new file mode 100644 index 0000000..fcd18be --- /dev/null +++ b/scripts/vela/vela.ini @@ -0,0 +1,80 @@ +; +; Copyright (c) 2021 Arm Limited. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; + +; ----------------------------------------------------------------------------- +; Vela configuration file + +; ----------------------------------------------------------------------------- +; System Configuration + +; Ethos-U55 Deep Embedded: SRAM (1.6 GB/s) and Flash (0.1 GB/s) +[System_Config.Ethos_U55_Deep_Embedded] +core_clock=200e6 +axi0_port=Sram +axi1_port=OffChipFlash +Sram_clock_scale=1.0 +Sram_burst_length=32 +Sram_read_latency=32 +Sram_write_latency=32 +OffChipFlash_clock_scale=0.0625 +OffChipFlash_burst_length=128 +OffChipFlash_read_latency=64 +OffChipFlash_write_latency=64 + +; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s) +[System_Config.Ethos_U55_High_End_Embedded] +core_clock=500e6 +axi0_port=Sram +axi1_port=OffChipFlash +Sram_clock_scale=1.0 +Sram_burst_length=32 +Sram_read_latency=32 +Sram_write_latency=32 +OffChipFlash_clock_scale=0.125 +OffChipFlash_burst_length=128 +OffChipFlash_read_latency=64 +OffChipFlash_write_latency=64 + +; ----------------------------------------------------------------------------- +; Memory Mode + +; SRAM Only: only one AXI port is used and the SRAM is used for all storage +[Memory_Mode.Sram_Only] +const_mem_area=Axi0 +arena_mem_area=Axi0 +cache_mem_area=Axi0 + +; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software +; The non-SRAM memory is assumed to be read-only +[Memory_Mode.Shared_Sram] +const_mem_area=Axi1 +arena_mem_area=Axi0 +cache_mem_area=Axi0 + +; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U +; The non-SRAM memory is assumed to be read-writeable +[Memory_Mode.Dedicated_Sram] +const_mem_area=Axi1 +arena_mem_area=Axi1 +cache_mem_area=Axi0 +cache_sram_size=393216 + +; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U +; The non-SRAM memory is assumed to be read-writeable +[Memory_Mode.Dedicated_Sram_512KB] +inherit=Memory_Mode.Dedicated_Sram +cache_sram_size=524288 |