diff options
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/sections/building.md | 2 | ||||
| -rw-r--r-- | docs/sections/testing_benchmarking.md | 6 |
2 files changed, 2 insertions, 6 deletions
diff --git a/docs/sections/building.md b/docs/sections/building.md index 699667b..5f8a3cb 100644 --- a/docs/sections/building.md +++ b/docs/sections/building.md @@ -206,7 +206,7 @@ The build parameters are: `ETHOS_U_NPU_ID` is `U65`. Default value is 393216 (see [default_vela.ini](../../scripts/vela/default_vela.ini) ). - `CPU_PROFILE_ENABLED`: Sets whether profiling information for the CPU core should be displayed. By default, this is - set to false, but can be turned on for FPGA targets. The the FVP and the CPU core cycle counts are not meaningful and + set to false, but can be turned on for FPGA targets. The FVP and the CPU core cycle counts are **not** meaningful and are not to be used. - `LOG_LEVEL`: Sets the verbosity level for the output of the application over `UART`, or `stdout`. Valid values are: diff --git a/docs/sections/testing_benchmarking.md b/docs/sections/testing_benchmarking.md index d1cd9df..2641049 100644 --- a/docs/sections/testing_benchmarking.md +++ b/docs/sections/testing_benchmarking.md @@ -101,11 +101,7 @@ INFO - NPU TOTAL cycles: 1081634 INFO - Profile for Inference: INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 628122 INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 135087 -INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 62870 -INFO - NPU ACTIVE cycles: 1081007 -INFO - NPU IDLE cycles: 626 -INFO - NPU TOTAL cycles: 1081634 -INFO - CPU ACTIVE cycles (approx): 993553 +... INFO - Time ms: 210 ``` |