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Diffstat (limited to 'docs/sections/testing_benchmarking.md')
| -rw-r--r-- | docs/sections/testing_benchmarking.md | 45 |
1 files changed, 33 insertions, 12 deletions
diff --git a/docs/sections/testing_benchmarking.md b/docs/sections/testing_benchmarking.md index 6350f52..d040d17 100644 --- a/docs/sections/testing_benchmarking.md +++ b/docs/sections/testing_benchmarking.md @@ -47,8 +47,6 @@ arm_ml_embedded_evaluation_kit-<use_case>-tests ```log INFO - native platform initialised -INFO - ARM Ethos-U55 Evaluation application for MPS3 FPGA Prototyping Board and FastModel - ... =============================================================================== All tests passed (37 assertions in 7 test cases) @@ -60,11 +58,24 @@ INFO - ARM Ethos-U55 Evaluation application for MPS3 FPGA Prototyping Board and Profiling is enabled by default when configuring the project. Profiling enables you to display: -- The active and idle NPU cycle counts when the Arm® *Ethos™-U55* is enabled. For more information, refer to the - `-DETHOS_U55_ENABLED` section in: [Build options](./building.md#build-options). +- NPU event counters when the Arm® *Ethos™-U* NPU is enabled (see `ETHOS_U_NPU_ENABLED` in [Build options](./building.md#build-options) ) + + - Total cycle: The number of NPU cycles + + - Active cycles: number of NPU cycles that were used for computation + + - Idle cycles: number of cycles for which the NPU was idle + + - AXI0 read beats: The number of AXI beats with read transactions from AXI0 bus. AXI0 is the bus where + *Ethos-U* NPU reads and writes to the computation buffers, activation buf, or tensor arenas. + + - AXI0 write beats: The number of AXI beats with write transactions to AXI0 bus. + + - AXI1 read beats: The number of AXI beats with read transactions from AXI1 bus. AXI1 is the bus where + *Ethos-U* NPU reads the model. So, read-only. + - If CPU profiling is enabled, the CPU cycle counts and the time elapsed, in milliseconds, for inferences performed. For - further information, please refer to the `-DCPU_PROFILE_ENABLED` section in: - [Build options](./building.md#build-options). + further information, please refer to the `CPU_PROFILE_ENABLED` in [Build options](./building.md#build-options). > **Note:** Only do this when running on a physical FPGA board as the FVP does not contain a cycle-approximate or > cycle-accurate *Cortex-M* model. @@ -74,18 +85,28 @@ For example: - On the FVP: ```log - Active NPU cycles: 5475412 - Idle NPU cycles: 702 +INFO - Profile for Inference: +INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 628122 +INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 135087 +INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 62870 +INFO - NPU ACTIVE cycles: 1081007 +INFO - NPU IDLE cycles: 626 +INFO - NPU TOTAL cycles: 1081634 ``` - For the MPS3 platform, the time duration in milliseconds is also reported when `-DCPU_PROFILE_ENABLED=1` is added to CMake configuration command, like so: ```log - Active NPU cycles: 5629033 - Idle NPU cycles: 1005276 - Active CPU cycles: 993553 (approx) - Time in ms: 210 +INFO - Profile for Inference: +INFO - NPU AXI0_RD_DATA_BEAT_RECEIVED beats: 628122 +INFO - NPU AXI0_WR_DATA_BEAT_WRITTEN beats: 135087 +INFO - NPU AXI1_RD_DATA_BEAT_RECEIVED beats: 62870 +INFO - NPU ACTIVE cycles: 1081007 +INFO - NPU IDLE cycles: 626 +INFO - NPU TOTAL cycles: 1081634 +INFO - CPU ACTIVE cycles (approx): 993553 +INFO - Time ms: 210 ``` The next section of the documentation refers to: [Memory Considerations](memory_considerations.md). |