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Diffstat (limited to 'docs/sections/building.md')
| -rw-r--r-- | docs/sections/building.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/sections/building.md b/docs/sections/building.md index 699667b..5f8a3cb 100644 --- a/docs/sections/building.md +++ b/docs/sections/building.md @@ -206,7 +206,7 @@ The build parameters are: `ETHOS_U_NPU_ID` is `U65`. Default value is 393216 (see [default_vela.ini](../../scripts/vela/default_vela.ini) ). - `CPU_PROFILE_ENABLED`: Sets whether profiling information for the CPU core should be displayed. By default, this is - set to false, but can be turned on for FPGA targets. The the FVP and the CPU core cycle counts are not meaningful and + set to false, but can be turned on for FPGA targets. The FVP and the CPU core cycle counts are **not** meaningful and are not to be used. - `LOG_LEVEL`: Sets the verbosity level for the output of the application over `UART`, or `stdout`. Valid values are: |