diff options
| author | Conor Kennedy <conor.kennedy@arm.com> | 2023-02-13 10:50:40 +0000 |
|---|---|---|
| committer | Conor Kennedy <conor.kennedy@arm.com> | 2023-02-13 15:47:33 +0000 |
| commit | 5cf8e74e702e3d5278c898202cc25b04b812d87a (patch) | |
| tree | d13ebf0a0a3bc7d7b8bce9dfdc8e77560bb92e71 /source/hal | |
| parent | 5b4fea129b2f738fc877916111908b955ad07d5a (diff) | |
| download | ml-embedded-evaluation-kit-5cf8e74e702e3d5278c898202cc25b04b812d87a.tar.gz | |
MLECO-2709: Inclusive language update
* Update various files to use inclusive language
Signed-off-by: Conor Kennedy <conor.kennedy@arm.com>
Change-Id: I538f61a400e1d58acb6397bb5e2ba3d912196314
Diffstat (limited to 'source/hal')
| -rw-r--r-- | source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c | 4 | ||||
| -rw-r--r-- | source/hal/source/components/lcd/source/lcd_img.c | 4 | ||||
| -rw-r--r-- | source/hal/source/platform/mps3/source/smm_mps3.h | 10 |
3 files changed, 9 insertions, 9 deletions
diff --git a/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c b/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c index 1a10bad..cfbb386 100644 --- a/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c +++ b/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -203,7 +203,7 @@ void GLCD_DrawChar( { unsigned int i, j, k, pixs; - /* Sanity check: out of bounds? */ + /* Heatlh check: out of bounds? */ if ((x + cw) > GLCD_WIDTH || (y + ch) > GLCD_HEIGHT) { return; } diff --git a/source/hal/source/components/lcd/source/lcd_img.c b/source/hal/source/components/lcd/source/lcd_img.c index d3ce260..752fe86 100644 --- a/source/hal/source/components/lcd/source/lcd_img.c +++ b/source/hal/source/components/lcd/source/lcd_img.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,7 +41,7 @@ int lcd_display_image(const uint8_t* data, const uint32_t width, const uint32_t pos_x, const uint32_t pos_y, const uint32_t downsample_factor) { - /* Sanity checks */ + /* Health checks */ assert(data); if ((pos_x + width/downsample_factor > GLCD_WIDTH) || (pos_y + height/downsample_factor > GLCD_HEIGHT)) { diff --git a/source/hal/source/platform/mps3/source/smm_mps3.h b/source/hal/source/platform/mps3/source/smm_mps3.h index e455975..8354c9c 100644 --- a/source/hal/source/platform/mps3/source/smm_mps3.h +++ b/source/hal/source/platform/mps3/source/smm_mps3.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -182,8 +182,8 @@ typedef struct */ __IO uint32_t CR1; /* Offset: 0x004 (R/W) Control register 1 * [31:4] : Reserved - * [3] : Slave-mode output disable - * [2] : Master or slave mode select + * [3] : Worker output disable + * [2] : Controller or worker mode select * [1] : Synchronous serial port enable * [0] : Loop back mode */ @@ -259,9 +259,9 @@ typedef struct #define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos) #define SSP_CR1_SSE_Pos 1 /* Serial port enable. */ #define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos) -#define SSP_CR1_MS_Pos 2 /* Master or Slave mode. */ +#define SSP_CR1_MS_Pos 2 /* Controller or worker mode. */ #define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos) -#define SSP_CR1_SOD_Pos 3 /* Slave Output mode Disable. */ +#define SSP_CR1_SOD_Pos 3 /* Secondary Output mode Disable. */ #define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos) /* SSP_SR Status register. */ |