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| author | Richard Burton <richard.burton@arm.com> | 2021-08-12 17:26:30 +0100 |
|---|---|---|
| committer | Richard Burton <richard.burton@arm.com> | 2021-08-12 17:26:30 +0100 |
| commit | 0d110594b8a50ce3311be5187f01de2e3b8fe995 (patch) | |
| tree | 1e56414f491f1bbd29df4912e2354ac5e1682133 /source/application/hal | |
| parent | d2b9853ca848f11dee55beedbb9d650763b3ed53 (diff) | |
| download | ml-embedded-evaluation-kit-0d110594b8a50ce3311be5187f01de2e3b8fe995.tar.gz | |
MLECO-1904: Update to use latest TFLu
* Now uses seperate TFLu github repo
* Fixes to align with API changes
* Update ASR model ops and re-enable ASR inference tests
* Set default release level to release_with_logs
Signed-off-by: Richard Burton <richard.burton@arm.com>
Change-Id: I57612088985dece1413c5c00a6e442381e07dd91
Diffstat (limited to 'source/application/hal')
| -rw-r--r-- | source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld index 8bb99cd..46fc2e5 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld @@ -65,7 +65,14 @@ SECTIONS .text.at_itcm : { KEEP(*(.vectors)) - *(.text*) + + /** + * All code goes here, with one exception of + * all_ops_resolver object file. This code + * instead placed on BRAM. See comment in the + * BRAM section for details. + **/ + *(EXCLUDE_FILE(*all_ops_resolver.o) .text*) KEEP(*(.init)) KEEP(*(.fini)) @@ -87,11 +94,6 @@ SECTIONS KEEP(*(.eh_frame*)) } > ITCM - .ARM.extab.at_itcm : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > ITCM - __exidx_start = .; .ARM.exidx.at_itcm : { @@ -208,6 +210,18 @@ SECTIONS KEEP(*(.jcr*)) . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + + /** + * Place the all ops resolver code data here. This accounts + * for ~4k worth of saving on the ITCM load region. It is + * only designed to be included (by default) for the inference + * runner use case. + **/ + *all_ops_resolver.o (*.text*) + . = ALIGN(4); + __data_end__ = .; } > BRAM |