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authorKshitij Sisodia <kshitij.sisodia@arm.com>2021-11-24 10:39:52 +0000
committerKshitij Sisodia <kshitij.sisodia@arm.com>2021-11-25 10:05:25 +0000
commit661959c6d2fabada5d465e9de8f84128e3f7b684 (patch)
tree3321ebb442c7ec1f7af454dd25d6bd1b54663587 /source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
parentb59ba684aef4bef16262a1825e787a55fc992f0d (diff)
downloadml-embedded-evaluation-kit-661959c6d2fabada5d465e9de8f84128e3f7b684.tar.gz
MLECO-2426: Support for new Corstone-300 app note AN552 rev B.
These changes will limit the use of FPGA internal SRAM from a max of 4MiB to 2MiB and the BRAM from 2MiB to 1MiB. Change-Id: I69c8e695aee26ff4f235bfe83ffd26efbd66f547
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld')
-rw-r--r--source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld6
1 files changed, 3 insertions, 3 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
index e5b6bd9..82cb18e 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
@@ -16,15 +16,15 @@
*/
__STACK_SIZE = 0x00060000;
-__HEAP_SIZE = 0x000f0000;
+__HEAP_SIZE = 0x000C0000;
/* System memory brief */
MEMORY
{
ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
- BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
- SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+ BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+ SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
}