diff options
author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2021-11-24 10:39:52 +0000 |
---|---|---|
committer | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2021-11-25 10:05:25 +0000 |
commit | 661959c6d2fabada5d465e9de8f84128e3f7b684 (patch) | |
tree | 3321ebb442c7ec1f7af454dd25d6bd1b54663587 /source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld | |
parent | b59ba684aef4bef16262a1825e787a55fc992f0d (diff) | |
download | ml-embedded-evaluation-kit-661959c6d2fabada5d465e9de8f84128e3f7b684.tar.gz |
MLECO-2426: Support for new Corstone-300 app note AN552 rev B.
These changes will limit the use of FPGA internal SRAM from a max
of 4MiB to 2MiB and the BRAM from 2MiB to 1MiB.
Change-Id: I69c8e695aee26ff4f235bfe83ffd26efbd66f547
Diffstat (limited to 'source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld')
-rw-r--r-- | source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld index bcbc81f..d369fa7 100644 --- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld +++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld @@ -16,15 +16,15 @@ */ __STACK_SIZE = 0x00060000; -__HEAP_SIZE = 0x000f0000; +__HEAP_SIZE = 0x000C0000; /* System memory brief */ MEMORY { ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 - BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000 - SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000 + BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000 DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 /* Dynamic load regions declared for use by FVP only |