diff options
author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2023-03-10 16:33:23 +0000 |
---|---|---|
committer | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2023-03-15 13:51:01 +0000 |
commit | 26bc923b15be6d1a1788f5afb26241b6fb89a718 (patch) | |
tree | 77e30b6d3a2b93c99f26e34e1e369d9cfa2dfc1b /scripts | |
parent | 987efaeca438b7a3ef0926edef28a22a5801af9f (diff) | |
download | ml-embedded-evaluation-kit-26bc923b15be6d1a1788f5afb26241b6fb89a718.tar.gz |
MLECO-3666: Updating to 23.02 dependencies.23.02-rc1
Updating dependency submodules to 23.02 versions.
See https://review.mlplatform.org/plugins/gitiles/ml/ethos-u/ethos-u/+/refs/tags/23.02/23.02.json
Change-Id: If0e396decadc1b4e3c6b263c65f75ccf0dafed28
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Diffstat (limited to 'scripts')
-rw-r--r-- | scripts/cmake/platforms/mps3/build_configuration.cmake | 12 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-debug.ld | 298 | ||||
-rw-r--r-- | scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-release.ld (renamed from scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld) | 0 | ||||
-rw-r--r-- | scripts/cmake/platforms/simple_platform/build_configuration.cmake | 14 | ||||
-rw-r--r-- | scripts/cmake/platforms/simple_platform/simple_platform_debug.ld | 291 | ||||
-rw-r--r-- | scripts/cmake/platforms/simple_platform/simple_platform_release.ld (renamed from scripts/cmake/platforms/simple_platform/simple_platform.ld) | 0 | ||||
-rw-r--r-- | scripts/cmake/tensorflow.cmake | 15 | ||||
-rw-r--r-- | scripts/cmake/toolchains/bare-metal-armclang.cmake | 6 | ||||
-rw-r--r-- | scripts/py/requirements.txt | 14 |
9 files changed, 633 insertions, 17 deletions
diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake index fd55fa8..1743253 100644 --- a/scripts/cmake/platforms/mps3/build_configuration.cmake +++ b/scripts/cmake/platforms/mps3/build_configuration.cmake @@ -1,5 +1,5 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,6 +49,16 @@ function(platform_custom_post_build) cmake_parse_arguments(PARSED "" "${oneValueArgs}" "" ${ARGN} ) set_target_properties(${PARSED_TARGET_NAME} PROPERTIES SUFFIX ".axf") + + # For GNU toolchain, we have different linker scripts for Debug and Release + # as the code footprint difference between the two is quite big. We do it + # only for SSE-300 as the main code memory is the ITCM which is limited to + # 512kiB. + if ((CMAKE_CXX_COMPILER_ID STREQUAL "GNU") AND (TARGET_SUBSYSTEM STREQUAL "sse-300")) + string(TOLOWER ${CMAKE_BUILD_TYPE} LINKER_SCRIPT_SUFFIX) + set(LINKER_SCRIPT_NAME "${LINKER_SCRIPT_NAME}-${LINKER_SCRIPT_SUFFIX}" PARENT_SCOPE FORCE) + endif() + # Add link options for the linker script to be used: add_linker_script( ${PARSED_TARGET_NAME} # Target diff --git a/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-debug.ld b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-debug.ld new file mode 100644 index 0000000..715cdeb --- /dev/null +++ b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-debug.ld @@ -0,0 +1,298 @@ +/* + * SPDX-FileCopyrightText: Copyright 2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +__STACK_SIZE = 0x00008000; +__HEAP_SIZE = 0x000C0000; + +/* System memory brief */ +MEMORY +{ + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 + BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000 + DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 + + /* Dynamic load regions declared for use by FVP only + * These regions are mentioned in the CMake subsystem profile. + * Do not change the addresses here in isolation. */ + DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000 + DDR_dynamic_ifm (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000 + DDR_dynamic_ofm (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions ITCM and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text.at_itcm : + { + KEEP(*(.vectors)) + + /** + * Any code that is not time sensitive can be excluded from here. + * This code is instead placed on BRAM. See comment in the BRAM + * section for details. + */ + *(EXCLUDE_FILE(*all_ops_resolver.o + *hal.c.obj + *_allocator.o + *flatbuffer*.o + *Profiler*.obj + *lcd*.obj + *timing_adapter.c.obj) + .text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + KEEP(*(.eh_frame*)) + } > ITCM + + __exidx_start = .; + .ARM.exidx.at_itcm : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ITCM + __exidx_end = .; + + .zero.table.at_itcm : + { + . = ALIGN(4); + __zero_table_start__ = .; + + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ + + __zero_table_end__ = .; + } > ITCM + + .copy.table.at_itcm : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Section to be copied - part 1: any data to be placed in BRAM */ + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */ + + /* Section to be copied - part 2: RO data for for DTCM */ + LONG (__etext2) + LONG (__ro_data_start__) + LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */ + + __copy_table_end__ = .; + } > ITCM + + __itcm_total = ALIGN(4); + + ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow") + + .sram : + { + . = ALIGN(16); + /* Cache area (if used) */ + *(.bss.NoInit.ethos_u_cache) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ + *(.bss.NoInit.activation_buf_sram) + . = ALIGN(16); + } > SRAM AT > SRAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > DTCM AT > DTCM + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + ASSERT( + (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM), + "DTCM overflow") + + .ddr.at_ddr : + { + /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. + * Force the alignment here as a workaround */ + . = ALIGN(16); + /* nn model's baked in input matrices */ + *(ifm) + . = ALIGN(16); + /* nn model's default space */ + *(nn_model) + . = ALIGN (16); + /* labels */ + *(labels) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ + *(activation_buf_dram) + . = ALIGN (16); + } > DDR AT > DDR + + .text.at_ddr : + { + . = ALIGN(4); + *Profiler*.obj (*.text*) + . = ALIGN(4); + } > DDR AT > DDR + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in DTCM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .bram.at_ddr : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + KEEP(*(.jcr*)) + . = ALIGN(4); + + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + + /** + * Place the all ops resolver code data here. This accounts + * for ~4k worth of saving on the ITCM load region. It is + * only designed to be included (by default) for the inference + * runner use case. + **/ + *all_ops_resolver.o (*.text*) + . = ALIGN(4); + *hal.c.obj (*.text*) + . = ALIGN(4); + *_allocator.o (*.text*) + . = ALIGN(4); + *flatbuffer*.o (*.text*) + . = ALIGN(4); + *lcd*.obj (*.text*) + . = ALIGN(4); + *timing_adapter.* (*.text*) + . = ALIGN(4); + + __data_end__ = .; + } > BRAM + + __etext2 = __etext + (__data_end__ - __data_start__); + + .data.at_ddr : AT (__etext2) + { + . = ALIGN(4); + __ro_data_start__ = .; + + *(.rodata*) + . = ALIGN(4); + * (npu_driver_version) + . = ALIGN(4); + * (npu_driver_arch_version) + . = ALIGN(4); + + __ro_data_end__ = .; + } > BRAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > BRAM + + ASSERT ( + (__ro_data_end__ - __ro_data_start__) + + (__data_end__ - __data_start__) + + __HEAP_SIZE <= LENGTH(BRAM), + "BRAM overflow") +} diff --git a/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-release.ld index 2d72ed9..2d72ed9 100644 --- a/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld +++ b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300-release.ld diff --git a/scripts/cmake/platforms/simple_platform/build_configuration.cmake b/scripts/cmake/platforms/simple_platform/build_configuration.cmake index 74b3896..3536c5b 100644 --- a/scripts/cmake/platforms/simple_platform/build_configuration.cmake +++ b/scripts/cmake/platforms/simple_platform/build_configuration.cmake @@ -1,5 +1,5 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ function(set_platform_global_defaults) set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake CACHE FILEPATH "Toolchain file") endif() + set(LINKER_SCRIPT_NAME "simple_platform" PARENT_SCOPE) set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/simple" PARENT_SCOPE) endfunction() @@ -30,8 +31,15 @@ function(platform_custom_post_build) cmake_parse_arguments(PARSED "" "${oneValueArgs}" "" ${ARGN} ) set_target_properties(${PARSED_TARGET_NAME} PROPERTIES SUFFIX ".axf") - # Add link options for the linker script to be used: + # For GNU toolchain, we have different linker scripts for Debug and Release + # as the code footprint difference between the two is quite big. + if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + string(TOLOWER ${CMAKE_BUILD_TYPE} LINKER_SCRIPT_SUFFIX) + set(LINKER_SCRIPT_NAME "${LINKER_SCRIPT_NAME}_${LINKER_SCRIPT_SUFFIX}" PARENT_SCOPE FORCE) + endif() + + # Add link options for the linker script to be used: add_linker_script( ${PARSED_TARGET_NAME} # Target ${CMAKE_SCRIPTS_DIR}/platforms/simple_platform # Directory path @@ -56,4 +64,4 @@ function(platform_custom_post_build) AXF_PATH ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.axf SECTION_PATTERNS "${LINKER_SECTION_TAGS}" OUTPUT_BIN_NAMES "${LINKER_OUTPUT_BIN_TAGS}") -endfunction()
\ No newline at end of file +endfunction() diff --git a/scripts/cmake/platforms/simple_platform/simple_platform_debug.ld b/scripts/cmake/platforms/simple_platform/simple_platform_debug.ld new file mode 100644 index 0000000..9a4f88a --- /dev/null +++ b/scripts/cmake/platforms/simple_platform/simple_platform_debug.ld @@ -0,0 +1,291 @@ +/* + * SPDX-FileCopyrightText: Copyright 2021,2023 Arm Limited and/or its affiliates <open-source-office@arm.com> + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +__STACK_SIZE = 0x00008000; +__HEAP_SIZE = 0x000C0000; + +/* System memory brief */ +MEMORY +{ + ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 + BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000 + DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions ITCM and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text.at_itcm : + { + KEEP(*(.vectors)) + + /** + * Any code that is not time sensitive can be excluded from here. + * This code is instead placed on BRAM. See comment in the BRAM + * section for details. + */ + *(EXCLUDE_FILE(*all_ops_resolver.o + *hal.c.obj + *_allocator.o + *flatbuffer*.o + *lcd*.obj + *Profiler*.obj + *timing_adapter.c.obj) + .text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + KEEP(*(.eh_frame*)) + } > ITCM + + __exidx_start = .; + .ARM.exidx.at_itcm : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ITCM + __exidx_end = .; + + .zero.table.at_itcm : + { + . = ALIGN(4); + __zero_table_start__ = .; + + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ + + __zero_table_end__ = .; + } > ITCM + + .copy.table.at_itcm : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Section to be copied - part 1: any data to be placed in BRAM */ + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */ + + /* Section to be copied - part 2: RO data for for DTCM */ + LONG (__etext2) + LONG (__ro_data_start__) + LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */ + + __copy_table_end__ = .; + } > ITCM + + __itcm_total = ALIGN(4); + + ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow") + + .sram : + { + . = ALIGN(16); + /* Cache area (if used) */ + *(.bss.NoInit.ethos_u_cache) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ + *(.bss.NoInit.activation_buf_sram) + . = ALIGN(16); + } > SRAM AT > SRAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > DTCM AT > DTCM + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + ASSERT( + (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM), + "DTCM overflow") + + .ddr.at_ddr : + { + /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. + * Force the alignment here as a workaround */ + . = ALIGN(16); + /* nn model's baked in input matrices */ + *(ifm) + . = ALIGN(16); + /* nn model's default space */ + *(nn_model) + . = ALIGN (16); + /* labels */ + *(labels) + . = ALIGN (16); + /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ + *(activation_buf_dram) + . = ALIGN (16); + } > DDR AT > DDR + + .text.at_ddr : + { + . = ALIGN(4); + *Profiler*.obj (*.text*) + . = ALIGN(4); + } > DDR AT > DDR + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in DTCM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .bram.at_ddr : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + KEEP(*(.jcr*)) + . = ALIGN(4); + + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + + /** + * Place the all ops resolver code data here. This accounts + * for ~4k worth of saving on the ITCM load region. It is + * only designed to be included (by default) for the inference + * runner use case. + **/ + *all_ops_resolver.o (*.text*) + . = ALIGN(4); + *hal.c.obj (*.text*) + . = ALIGN(4); + *_allocator.o (*.text*) + . = ALIGN(4); + *flatbuffer*.o (*.text*) + . = ALIGN(4); + *lcd*.obj (*.text*) + . = ALIGN(4); + *timing_adapter.* (*.text*) + . = ALIGN(4); + + __data_end__ = .; + } > BRAM + + __etext2 = __etext + (__data_end__ - __data_start__); + + .data.at_ddr : AT (__etext2) + { + . = ALIGN(4); + __ro_data_start__ = .; + + *(.rodata*) + . = ALIGN(4); + * (npu_driver_version) + . = ALIGN(4); + * (npu_driver_arch_version) + . = ALIGN(4); + + __ro_data_end__ = .; + } > BRAM + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > BRAM + + ASSERT ( + (__ro_data_end__ - __ro_data_start__) + + (__data_end__ - __data_start__) + + __HEAP_SIZE <= LENGTH(BRAM), + "BRAM overflow") +} diff --git a/scripts/cmake/platforms/simple_platform/simple_platform.ld b/scripts/cmake/platforms/simple_platform/simple_platform_release.ld index 492f6da..492f6da 100644 --- a/scripts/cmake/platforms/simple_platform/simple_platform.ld +++ b/scripts/cmake/platforms/simple_platform/simple_platform_release.ld diff --git a/scripts/cmake/tensorflow.cmake b/scripts/cmake/tensorflow.cmake index ea3b320..8d52765 100644 --- a/scripts/cmake/tensorflow.cmake +++ b/scripts/cmake/tensorflow.cmake @@ -49,6 +49,12 @@ set(TENSORFLOW_LITE_MICRO_PATH "${TENSORFLOW_SRC_PATH}/tensorflow/lite/micro") set(TENSORFLOW_LITE_MICRO_GENDIR ${CMAKE_CURRENT_BINARY_DIR}/tensorflow/) set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME "libtensorflow-microlite.a") +# Add virtual environment's Python directory path to the system path. +# NOTE: This path is passed to the TensorFlow Lite Micro's make env +# as it depends on some basic Python packages (like Pillow) installed +# and the system-wide Python installation might not have them. +set(ENV_PATH "${PYTHON_VENV}/bin:$ENV{PATH}") + if (TARGET_PLATFORM STREQUAL native) set(TENSORFLOW_LITE_MICRO_TARGET "linux") set(TENSORFLOW_LITE_MICRO_TARGET_ARCH x86_64) @@ -73,7 +79,8 @@ endif() if (TENSORFLOW_LITE_MICRO_CLEAN_DOWNLOADS) message(STATUS "Refreshing TensorFlow Lite Micro's third party downloads...") execute_process( - COMMAND make -f ${TENSORFLOW_LITE_MICRO_PATH}/tools/make/Makefile clean_downloads third_party_downloads + COMMAND ${CMAKE_COMMAND} -E env PATH=${ENV_PATH} + make -f ${TENSORFLOW_LITE_MICRO_PATH}/tools/make/Makefile clean_downloads third_party_downloads RESULT_VARIABLE return_code WORKING_DIRECTORY ${TENSORFLOW_SRC_PATH}) if (NOT return_code EQUAL "0") @@ -91,12 +98,6 @@ endif() list(APPEND MAKE_TARGETS_LIST "microlite") message(STATUS "TensorFlow Lite Micro build to be called for these targets: ${MAKE_TARGETS_LIST}") -# Add virtual environment's Python directory path to the system path. -# NOTE: This path is passed to the TensorFlow Lite Micro's make env -# as it depends on some basic Python packages (like Pillow) installed -# and the system-wide Python installation might not have them. -set(ENV_PATH "${PYTHON_VENV}/bin:$ENV{PATH}") - # Commands and targets add_custom_target(tensorflow_build ALL diff --git a/scripts/cmake/toolchains/bare-metal-armclang.cmake b/scripts/cmake/toolchains/bare-metal-armclang.cmake index 036e67b..f829762 100644 --- a/scripts/cmake/toolchains/bare-metal-armclang.cmake +++ b/scripts/cmake/toolchains/bare-metal-armclang.cmake @@ -1,5 +1,5 @@ #---------------------------------------------------------------------------- -# SPDX-FileCopyrightText: Copyright 2021 - 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> +# SPDX-FileCopyrightText: Copyright 2021 - 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -70,6 +70,10 @@ elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m33) # Flags for cortex-m33 to go here endif() +if (NOT DEFINED MIN_ARM_CLANG_VERSION) + set(MIN_ARM_CLANG_VERSION 6.16) +endif() + set(${CPU_COMPILE_DEF} 1) # Warning options diff --git a/scripts/py/requirements.txt b/scripts/py/requirements.txt index 20276d8..e75626c 100644 --- a/scripts/py/requirements.txt +++ b/scripts/py/requirements.txt @@ -1,13 +1,17 @@ cffi==1.15.0 +cmake==3.25.2 +flatbuffers==2.0.7 +importlib-metadata==6.0.0 Jinja2==2.11.2 -llvmlite==0.38.0 +llvmlite==0.39.1 +lxml==4.9.2 MarkupSafe==2.0.1 -numba==0.55.1 -numpy==1.21.3 +numba==0.56.4 +numpy==1.23.5 Pillow==9.2.0 pycparser==2.20 resampy==0.3.1 -scipy==1.7.3 +scipy==1.10.1 six==1.16.0 SoundFile==0.10.3.post1 -cmake==3.23.3 +zipp==3.15.0 |