diff options
author | Cisco Cervellera <cisco.cervellera@arm.com> | 2021-08-02 09:32:07 +0100 |
---|---|---|
committer | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-08-03 16:10:16 +0100 |
commit | f085fa5a2859178741f39563b4d9d68ca41d916a (patch) | |
tree | 62fd8411c63a853be4c32683a3ada0b6affb0399 /scripts | |
parent | 81c4c9178598e5c26af7373eca67842a8fe4179f (diff) | |
download | ml-embedded-evaluation-kit-f085fa5a2859178741f39563b4d9d68ca41d916a.tar.gz |
MLECO-2051: Work with Corstone-300 + Ethos-U65
Change-Id: I64ab930a1de5210f435f91bed7600a700581946f
Signed-off-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-on: https://eu-gerrit-2.euhpc.arm.com/c/ml/ecosystem/ml-embedded-evaluation-kit/+/459126
Tested-by: mlecosys <mlecosys@arm.com>
Tested-by: George Gekov <george.gekov@arm.com>
Reviewed-by: George Gekov <george.gekov@arm.com>
Reviewed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Diffstat (limited to 'scripts')
-rw-r--r-- | scripts/cmake/bare-metal-sources.cmake | 10 | ||||
-rw-r--r-- | scripts/cmake/native-sources.cmake | 6 | ||||
-rw-r--r-- | scripts/cmake/subsystem-profiles/corstone-sse-300.cmake | 22 | ||||
-rw-r--r-- | scripts/cmake/subsystem-profiles/simple_platform.cmake | 18 | ||||
-rw-r--r-- | scripts/cmake/templates/peripheral_memmap.h.template | 12 | ||||
-rw-r--r-- | scripts/cmake/tensorflow.cmake | 4 | ||||
-rw-r--r-- | scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake (renamed from scripts/cmake/ta_config.cmake) | 4 | ||||
-rw-r--r-- | scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake | 64 | ||||
-rw-r--r-- | scripts/vela/default_vela.ini | 14 |
9 files changed, 115 insertions, 39 deletions
diff --git a/scripts/cmake/bare-metal-sources.cmake b/scripts/cmake/bare-metal-sources.cmake index 95950df..d3dad41 100644 --- a/scripts/cmake/bare-metal-sources.cmake +++ b/scripts/cmake/bare-metal-sources.cmake @@ -36,10 +36,10 @@ set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/ set(LINKER_SCRIPT_DIR "${PLAT_HAL}/bsp/mem_layout") set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME "libtensorflow-microlite.a") set(TENSORFLOW_LITE_MICRO_FLAG "-DTF_LITE_STATIC_MEMORY") -set(ETHOS_U55_FLAG "-DARM_NPU=1") +set(ETHOS_U_NPU_FLAG "-DARM_NPU=1") -if (ETHOS_U55_ENABLED) - set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} ${ETHOS_U55_FLAG}") +if (ETHOS_U_NPU_ENABLED) + set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} ${ETHOS_U_NPU_FLAG}") endif () # Set specific flags depending on target platform and subsystem @@ -85,9 +85,9 @@ endif () # Add link options for the linker script to be used: add_linker_script(${LINKER_SCRIPT_DIR} ${LINKER_SCRIPT_NAME}) -if (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) USER_OPTION(TA_CONFIG_FILE "Path to the timing adapter configuration file" - "${CMAKE_SCRIPTS_DIR}/ta_config.cmake" + "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u55_high_end.cmake" FILEPATH) # must be included after target subsystem CMake file diff --git a/scripts/cmake/native-sources.cmake b/scripts/cmake/native-sources.cmake index dc8f263..2a5b0ae 100644 --- a/scripts/cmake/native-sources.cmake +++ b/scripts/cmake/native-sources.cmake @@ -18,11 +18,11 @@ set(CMAKE_INSTALL_PREFIX ${CMAKE_SOURCE_DIR}/build_native) set(PLAT_HAL ${CMAKE_CURRENT_SOURCE_DIR}/source/application/hal/platforms/native) -if (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) message(WARNING "EthosU can't be enabled for native builds." - "Use -DETHOS_U55_ENABLED=0 flag for this target platform." + "Use -DETHOS_U_NPU_ENABLED=0 flag for this target platform." "Overriding, disabling use of EthosU...") - set(ETHOS_U55_ENABLED OFF) + set(ETHOS_U_NPU_ENABLED OFF) endif() if (DEFINED LOG_LEVEL) diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake index 8b565fe..c87dd6a 100644 --- a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake +++ b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake @@ -96,11 +96,11 @@ set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3") set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ") set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ") -if (ETHOS_U55_ENABLED) - set(ETHOS_U55_BASE "0x48102000" CACHE STRING "Ethos-U55 base address") - set(ETHOS_U55_TA0_BASE "0x48103000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(ETHOS_U55_TA1_BASE "0x48103200" CACHE STRING "Ethos-U55's timing adapter 1 base address") -endif (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) + set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif (ETHOS_U_NPU_ENABLED) set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ") set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ") @@ -156,11 +156,11 @@ set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address") set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ") set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ") -if (ETHOS_U55_ENABLED) - set(SEC_ETHOS_U55_BASE "0x58102000" CACHE STRING "Ethos-U55 base address") - set(SEC_ETHOS_U55_TA0_BASE "0x58103000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(SEC_ETHOS_U55_TA1_BASE "0x58103200" CACHE STRING "Ethos-U55's timing adapter 1 base address") -endif (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) + set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") + set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") +endif (ETHOS_U_NPU_ENABLED) set(SEC_MPS3_I2C0_BASE "0x58200000" CACHE STRING "Touch Screen I2C Base Address ") set(SEC_MPS3_I2C1_BASE "0x58201000" CACHE STRING "Audio Interface I2C Base Address ") @@ -243,7 +243,7 @@ set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ") set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ") -if (ETHOS_U55_ENABLED) +if (ETHOS_U_NPU_ENABLED) set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ") endif () diff --git a/scripts/cmake/subsystem-profiles/simple_platform.cmake b/scripts/cmake/subsystem-profiles/simple_platform.cmake index c5e9d59..69a69b5 100644 --- a/scripts/cmake/subsystem-profiles/simple_platform.cmake +++ b/scripts/cmake/subsystem-profiles/simple_platform.cmake @@ -34,18 +34,18 @@ set(DESIGN_NAME "Simple platform" CACHE STRING "Design name") ################################################################################################### set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address") -if (ETHOS_U55_ENABLED) - set(ETHOS_U55_BASE "0x48102000" CACHE STRING "Ethos-U55 base address") - set(ETHOS_U55_TA0_BASE "0x48103000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(ETHOS_U55_TA1_BASE "0x48103200" CACHE STRING "Ethos-U55's timing adapter 1 base address") - set(SEC_ETHOS_U55_BASE "0x58102000" CACHE STRING "Ethos-U55 base address") - set(SEC_ETHOS_U55_TA0_BASE "0x58103000" CACHE STRING "Ethos-U55's timing adapter 0 base address") - set(SEC_ETHOS_U55_TA1_BASE "0x58103200" CACHE STRING "Ethos-U55's timing adapter 1 base address") +if (ETHOS_U_NPU_ENABLED) + set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address") + set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") + set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address") + set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address") + set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address") endif () ################################################################################################### # IRQ numbers # ################################################################################################### -if (ETHOS_U55_ENABLED) - set(EthosU_IRQn "56" CACHE STRING "Ethos-U55 Interrupt") +if (ETHOS_U_NPU_ENABLED) + set(EthosU_IRQn "56" CACHE STRING "Ethos-U NPU Interrupt") endif () diff --git a/scripts/cmake/templates/peripheral_memmap.h.template b/scripts/cmake/templates/peripheral_memmap.h.template index 050d7d7..a8c883c 100644 --- a/scripts/cmake/templates/peripheral_memmap.h.template +++ b/scripts/cmake/templates/peripheral_memmap.h.template @@ -67,9 +67,9 @@ #cmakedefine CMSDK_UART2_BASE (@CMSDK_UART2_BASE@) /* UART 2 Base Address */ #cmakedefine CMSDK_UART3_BASE (@CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/ -#cmakedefine ETHOS_U55_BASE (@ETHOS_U55_BASE@) /* Ethos-U55 base address*/ -#cmakedefine ETHOS_U55_TA0_BASE (@ETHOS_U55_TA0_BASE@) /* Ethos-U55's timing adapter 0 base address */ -#cmakedefine ETHOS_U55_TA1_BASE (@ETHOS_U55_TA1_BASE@) /* Ethos-U55's timing adapter 1 base address */ +#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ #cmakedefine CMSDK_UART4_BASE (@CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/ #cmakedefine CMSDK_UART5_BASE (@CMSDK_UART5_BASE@) /* UART 5 Base Address */ @@ -140,9 +140,9 @@ #cmakedefine SEC_SMSC9220_BASE (@SEC_SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */ #cmakedefine SEC_USB_BASE (@SEC_USB_BASE@) /* USB Base Address */ -#cmakedefine SEC_ETHOS_U55_BASE (@SEC_ETHOS_U55_BASE@) /* Ethos-U55 base address*/ -#cmakedefine SEC_ETHOS_U55_TA0_BASE (@SEC_ETHOS_U55_TA0_BASE@) /* Ethos-U55's timing adapter 0 base address */ -#cmakedefine SEC_ETHOS_U55_TA1_BASE (@SEC_ETHOS_U55_TA1_BASE@) /* Ethos-U55's timing adapter 1 base address */ +#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/ +#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */ +#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */ #cmakedefine SEC_USER_BASE (@SEC_USER_BASE@) /* User ? Base Address */ diff --git a/scripts/cmake/tensorflow.cmake b/scripts/cmake/tensorflow.cmake index 1123c7f..d0654b8 100644 --- a/scripts/cmake/tensorflow.cmake +++ b/scripts/cmake/tensorflow.cmake @@ -69,7 +69,7 @@ if (TARGET_PLATFORM STREQUAL native) else() set(TENSORFLOW_LITE_MICRO_TARGET "cortex_m_ethos_eval") set(TENSORFLOW_LITE_MICRO_TARGET_ARCH ${CMAKE_SYSTEM_PROCESSOR}${CPU_FEATURES}) - if(ETHOS_U55_ENABLED) + if(ETHOS_U_NPU_ENABLED) # Arm Ethos-U55 NPU is the co-processor for ML workload: set(TENSORFLOW_LITE_MICRO_CO_PROCESSOR "ethos_u") endif() @@ -104,7 +104,7 @@ add_custom_target(tensorflow_build ALL TARGET=${TENSORFLOW_LITE_MICRO_TARGET} TARGET_ARCH=${TENSORFLOW_LITE_MICRO_TARGET_ARCH} BUILD_TYPE=${TENSORFLOW_LITE_MICRO_BUILD_TYPE} - ETHOSU_DRIVER_PATH=${ETHOS_U55_DRIVER_SRC_PATH} + ETHOSU_DRIVER_PATH=${ETHOS_U_NPU_DRIVER_SRC_PATH} CMSIS_PATH=${CMSIS_SRC_PATH} # Conditional arguments diff --git a/scripts/cmake/ta_config.cmake b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake index 427884c..30e1516 100644 --- a/scripts/cmake/ta_config.cmake +++ b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake @@ -20,8 +20,8 @@ # NPU core with two AXIs). #---------------------------------------------------------------------------- -set(TA0_BASE "${SEC_ETHOS_U55_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address") -set(TA1_BASE "${SEC_ETHOS_U55_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address") +set(TA0_BASE "${SEC_ETHOS_U_NPU_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address") +set(TA1_BASE "${SEC_ETHOS_U_NPU_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address") message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") diff --git a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake new file mode 100644 index 0000000..d1fdc00 --- /dev/null +++ b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake @@ -0,0 +1,64 @@ +#---------------------------------------------------------------------------- +# Copyright (c) 2021 Arm Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +#---------------------------------------------------------------------------- + +#---------------------------------------------------------------------------- +# CMake description file for the Ethos-U55 Timing Adapter settings (single +# NPU core with two AXIs). +#---------------------------------------------------------------------------- + +set(TA0_BASE "${SEC_ETHOS_U_NPU_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address") +set(TA1_BASE "${SEC_ETHOS_U_NPU_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address") + +message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.") + +# Timing adapter settings for AXI0 +set(TA0_MAXR "16" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(TA0_MAXW "16" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(TA0_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(TA0_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(TA0_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(TA0_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(TA0_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(TA0_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(TA0_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(TA0_PERFCNT "0" CACHE STRING "32-bit event counter") +set(TA0_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; + Bit 1: 1=enable random AR reordering (0=default); + Bit 2: 1=enable random R reordering (0=default); + Bit 3: 1=enable random B reordering (0=default); + Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") +set(TA0_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(TA0_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") + +# Timing adapter settings for AXI1 +set(TA1_MAXR "24" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite") +set(TA1_MAXW "112" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite") +set(TA1_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite") +set(TA1_RLATENCY "500" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.") +set(TA1_WLATENCY "250" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.") +set(TA1_PULSE_ON "4000" CACHE STRING "No. of cycles addresses let through (0-65535).") +set(TA1_PULSE_OFF "1000" CACHE STRING "No. of cycles addresses blocked (0-65535).") +set(TA1_BWCAP "1172" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite") +set(TA1_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default") +set(TA1_PERFCNT "0" CACHE STRING "32-bit event counter") +set(TA1_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun; + Bit 1: 1=enable random AR reordering (0=default); + Bit 2: 1=enable random R reordering (0=default); + Bit 3: 1=enable random B reordering (0=default); + Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed") +set(TA1_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.") +set(TA1_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.") diff --git a/scripts/vela/default_vela.ini b/scripts/vela/default_vela.ini index 327b760..884b057 100644 --- a/scripts/vela/default_vela.ini +++ b/scripts/vela/default_vela.ini @@ -34,7 +34,19 @@ OffChipFlash_clock_scale=0.125 OffChipFlash_burst_length=128 OffChipFlash_read_latency=64 OffChipFlash_write_latency=64 - +; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s) +[System_Config.Ethos_U65_High_End] +core_clock=1e9 +axi0_port=Sram +axi1_port=Dram +Sram_clock_scale=1.0 +Sram_burst_length=32 +Sram_read_latency=32 +Sram_write_latency=32 +Dram_clock_scale=0.234375 +Dram_burst_length=128 +Dram_read_latency=500 +Dram_write_latency=250 ; ----------------------------------------------------------------------------- ; Memory Mode |