MLECO-3321: Updated TensorFlow Lite Micro.

Updated to latest version of TensorFlow Lite Micro and
removed forcing TENSORFLOW_LITE_MICRO_TARGET_ARCH to
Arm Cortex-M55 for SSE-310 (now it is correctly set to
Cortex-M85 instead).

Change-Id: Ib1e8680a8d2ea803e0e003032119a10b1d71754e
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>

1 files changed, 15 insertions, 9 deletions

diff --git a/docs/sections/timing_adapters.md b/docs/sections/timing_adapters.md
index 7ca7076..5db38c6 100644
--- a/docs/sections/timing_adapters.md
+++ b/docs/sections/timing_adapters.md
@@ -1,9 +1,9 @@
-# Building timing adapter with custom options
+# Timing adapter
 
-The sources contain the configuration for a timing adapter utility for the *Arm® Ethos™-U* NPU driver. The timing
-adapter allows the platform to simulate user provided memory bandwidth and latency constraints on platforms that
-support it. The timing adapter driver aims to control the behavior of two AXI buses used by *Ethos-U* NPU. One is for
-SRAM memory region, and the other is for flash or DRAM.
+The sources contain the configuration for a `Timing Adapter (TA)` utility for the *Arm® Ethos™-U* NPU driver. The
+timing adapter allows the platform to simulate user provided memory bandwidth and latency constraints on platforms that
+support it. It aims to control the behavior of two AXI buses used by *Ethos-U* NPU - one is for SRAM memory region, and
+the other is for flash or DRAM.
 
 The SRAM is where intermediate buffers are expected to be allocated and therefore, this region can serve frequent read
 and write traffic generated by computation operations while executing a neural network inference. The flash or DDR is
@@ -19,6 +19,8 @@ It is used for MPS3 FPGA and for Fast Model environment (or [AVH](./arm_virtual_
 > benchmarking for different bandwidth and latency conditions, we recommend using the Arm® Corstone™-300
 > implementations.
 
+## Building timing adapter with custom options
+
 The CMake build framework allows the parameters to control the behavior of each bus with following parameters:
 
 - `MAXR`: Maximum number of pending read operations allowed. `0` is inferred as infinite and the default value is `4`.
@@ -140,14 +142,17 @@ Corstone-300 FVP and FPGA implements timing adapters that are tied to AXI master
 Corstone-310 **FPGA** implements timing adapter blocks differently and those are placed on each of the main
 memories present on FPGA: SRAM, QSPI flash, DDR and user memory.
 Moreover, this timer adapter placement does not translate well to FVP, so current Corstone-310 FVP implementation does
-not support the feature. Additionally - base addresses of timer adapters blocks have changed for Corestone-310:
+not support the feature. Additionally - base addresses of timer adapters blocks have changed for Corstone-310.
+
+### Timer Adapters for Corstone-300 FVP and FPGA:
 
-#### Timer Adapters for Corstone-300 FVP and FPGA:
 | TA# | Interface TA is placed on | Base address (non-secure/secure) | Size  |
 |-----|---------------------------|----------------------------------|-------|
 | 0   | M0/AXI0 for Ethos-U NPU   | 0x4810_3000/0x5810_3000          | 0.5KB |
 | 1   | M1/AXI1 for Ethos-U NPU   | 0x4810_3200/0x5810_3200          | 0.5KB |
-#### Timer Adapter for Corstone-310 FPGA:
+
+### Timer Adapter for Corstone-310 FPGA:
+
 | TA# | Interface TA is placed on | Base address (non-secure/secure) | Size |
 |-----|---------------------------|----------------------------------|------|
 | 0   | FPGA SRAM                 | 0x4170_0000/0x5170_0000          | 4KB  |
@@ -155,4 +160,5 @@ not support the feature. Additionally - base addresses of timer adapters blocks
 | 2   | DDR                       | 0x4170_1000/0x5170_2000          | 4KB  |
 | 3   | User memory               | 0x4170_3000/0x5170_3000          | 4KB  |
 
-With this in mind, when targeting Corstone-310, evaluation kit should be built with timing adapters disabled altogether via `-DETHOS_U_NPU_TIMING_ADAPTER_ENABLED=OFF` flag. Because timing adapters do not affect CPU-driven traffic for Corstone-300, building both platforms without the support for timing adapters allows for a CPU performance comparison.
\ No newline at end of file
+This is why the evaluation kit is configured with timing adapters disabled altogether (parameter
+`ETHOS_U_NPU_TIMING_ADAPTER_ENABLED` set to `OFF`) for Corstone-310 target platform.