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| author | Kshitij Sisodia <kshitij.sisodia@arm.com> | 2021-05-27 13:57:35 +0100 |
|---|---|---|
| committer | Isabella Gottardi <isabella.gottardi@arm.com> | 2021-05-27 16:27:44 +0100 |
| commit | b9e9c899dcbbe35cac72bceb117ae4ec56494d81 (patch) | |
| tree | 5984a5ba1453c09e55094f9971e0b244169287a6 /docs/sections/appendix.md | |
| parent | 698c5a7316044c64ed98500a9a602554c69c9f3f (diff) | |
| download | ml-embedded-evaluation-kit-b9e9c899dcbbe35cac72bceb117ae4ec56494d81.tar.gz | |
MLECO-1943: Documentation review
Major update for the documentation. Also, a minor logging
change in helper scripts.
Change-Id: Ia79f78a45c9fa2d139418fbc0ca9e52245704ba3
Diffstat (limited to 'docs/sections/appendix.md')
| -rw-r--r-- | docs/sections/appendix.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/sections/appendix.md b/docs/sections/appendix.md index fe8e85d..555560f 100644 --- a/docs/sections/appendix.md +++ b/docs/sections/appendix.md @@ -2,7 +2,7 @@ ## Arm® Cortex®-M55 Memory map overview for Corstone™-300 reference design -The table below is the memory mapping information specific to the Arm® Cortex®-M55. +The following table refers to the memory mapping information specific to the Arm® Cortex®-M55. | Name | Base address | Limit address | Size | IDAU | Remarks | |-------|--------------|---------------|-----------|------|-----------------------------------------------------------| @@ -17,4 +17,4 @@ The table below is the memory mapping information specific to the Arm® Cortex® | SRAM | 0x3100_0000 | 0x313F_FFFF | 4 MiB | S | 2 banks of 2 MiB each as SSE-300 internal SRAM region | | DDR | 0x7000_0000 | 0x7FFF_FFFF | 256 MiB | S | DDR memory region | -Default memory map can be found here: <https://developer.arm.com/documentation/101051/0002/Memory-model/Memory-map>. +The default memory map can be found here: <https://developer.arm.com/documentation/101051/0002/Memory-model/Memory-map>. |