Fix documentation.

* Fix broken link "building-for-different-ethos_u-npu-variants"
* Corstone-300 + Ethos-U65 NPU support in memory_considerations

Signed-off-by: Isabella Gottardi <isabella.gottardi@arm.com>
Change-Id: I2e99e2d24d3cd0bb64e06481862660d1b0679f20

11 files changed, 20 insertions, 20 deletions

diff --git a/docs/documentation.md b/docs/documentation.md
index d9286a9..c1b1f3b 100644
--- a/docs/documentation.md
+++ b/docs/documentation.md
@@ -256,7 +256,7 @@ For further information, please see:
   - [Add custom inputs](./sections/building.md#add-custom-inputs)
   - [Add custom model](./sections/building.md#add-custom-model)
   - [Optimize custom model with Vela compiler](./sections/building.md#optimize-custom-model-with-vela-compiler)
-  - [Building for different Ethos-U NPU variants](#building-for-different-ethos-u-npu-variants)
+  - [Building for different Ethos-U NPU variants](./sections/building.md#building-for-different-ethos_u-npu-variants)
   - [Automatic file generation](./sections/building.md#automatic-file-generation)
 
 ## Deployment
diff --git a/docs/sections/building.md b/docs/sections/building.md
index 8bc03a3..0d6361b 100644
--- a/docs/sections/building.md
+++ b/docs/sections/building.md
@@ -22,7 +22,7 @@
   - [Add custom inputs](#add-custom-inputs)
   - [Add custom model](#add-custom-model)
   - [Optimize custom model with Vela compiler](#optimize-custom-model-with-vela-compiler)
-  - [Building for different Ethos-U NPU variants](#building-for-different-ethos-u-npu-variants)
+  - [Building for different Ethos-U NPU variants](#building-for-different-ethos_u-npu-variants)
   - [Automatic file generation](#automatic-file-generation)
 
 This section assumes that you are using an **x86 Linux** build machine.
diff --git a/docs/sections/memory_considerations.md b/docs/sections/memory_considerations.md
index 970be3a..a89175a 100644
--- a/docs/sections/memory_considerations.md
+++ b/docs/sections/memory_considerations.md
@@ -16,20 +16,20 @@ This section provides useful details on how the Machine Learning use-cases of th
 
 Although the guidance provided here is concerning the Arm® *Corstone™-300* system, it is fairly generic and is
 applicable for other platforms too. The Arm® *Corstone™-300* is composed of both the Arm® *Cortex™-M55* and the Arm®
-*Ethos™-U55*. The memory map for the Arm® *Cortex™-M55* core can be found in the [Appendix](./appendix.md).
+*Ethos™-U* NPU. The memory map for the Arm® *Cortex™-M55* core can be found in the [Appendix](./appendix.md).
 
-The Arm® *Ethos™-U55* NPU interacts with the system through two AXI interfaces. The first one, is envisaged to be the
+The Arm® *Ethos™-U* NPU interacts with the system through two AXI interfaces. The first one, is envisaged to be the
 higher-bandwidth, lower-latency, interface. In a typical system, this is wired to an SRAM as it is required to service
 frequent Read and Write traffic.
 
 The second interface is expected to have a higher-latency, lower-bandwidth characteristic, and is typically wired to a
-flash device servicing read-only traffic. In this configuration, the Arm® *Cortex™-M55* CPU and Arm® *Ethos™-U55* NPU
+flash device servicing read-only traffic. In this configuration, the Arm® *Cortex™-M55* CPU and Arm® *Ethos™-U* NPU
 read the contents of the neural network model, or the `.tflite` file, from the flash memory region. With the Arm®
-*Ethos™-U55* requesting these read transactions over its second AXI bus.
+*Ethos™-U* NPU requesting these read transactions over its second AXI bus.
 
 The input and output tensors, along with any intermediate computation buffers, are placed on SRAM. Therefore, both the
-Arm® *Cortex™-M55* CPU and Arm® *Ethos™-U55* NPU would be reading, or writing, to this region when running an inference.
-The Arm® *Ethos™-U55* NPU requests these Read and Write transactions over the first AXI bus.
+Arm® *Cortex™-M55* CPU and Arm® *Ethos™-U* NPU would be reading, or writing, to this region when running an inference.
+The Arm® *Ethos™-U* NPU requests these Read and Write transactions over the first AXI bus.
 
 ## Understanding memory usage from Vela output
 
@@ -177,7 +177,7 @@ LOAD_REGION_0       0x00000000                  0x00080000
     ; SSE-300's internal SRAM of 4MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
-    ; both Cortex-M55 and Ethos-U55
+    ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
     isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
     {
@@ -234,10 +234,10 @@ LOAD_REGION_1       0x70000000                  0x02000000
 ```
 
 > **Note:** With Arm® *Corstone™-300* FPGA and FVP implementations, only the BRAM, internal SRAM, and DDR memory regions
-> are accessible to the Arm® Ethos™-U55 NPU block.
+> are accessible to the Arm® Ethos™-U NPU block.
 
 In the preceding snippet, the internal SRAM region memory is utilized by the activation buffers with a limit of 4MiB. If
-used by a Vela optimized neural network model, then the Arm® *Ethos™-U55* NPU writes to this block frequently.
+used by a Vela optimized neural network model, then the Arm® *Ethos™-U* NPU writes to this block frequently.
 
 A bigger region of memory for storing the neural network model is placed in the DDR, or flash, region under
 `LOAD_REGION_1`. The two load regions are necessary as the motherboard configuration controller of the MPS3 limits the
diff --git a/docs/use_cases/ad.md b/docs/use_cases/ad.md
index 1a16a83..a8476bd 100644
--- a/docs/use_cases/ad.md
+++ b/docs/use_cases/ad.md
@@ -134,7 +134,7 @@ For additional information, please refer to:
 - [Using Arm Compiler](../sections/building.md#using-arm-compiler)
 - [Configuring the build for simple_platform](../sections/building.md#configuring-the-build-for-simple_platform)
 - [Working with model debugger from Arm Fast Model Tools](../sections/building.md#working-with-model-debugger-from-arm-fast-model-tools)
-- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos-u-npu-variants)
+- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos_u-npu-variants)
 
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and then
 > re-run the CMake command.
diff --git a/docs/use_cases/asr.md b/docs/use_cases/asr.md
index fb62afa..0969b63 100644
--- a/docs/use_cases/asr.md
+++ b/docs/use_cases/asr.md
@@ -181,7 +181,7 @@ For further information, please refer to:
 - [Using Arm Compiler](../sections/building.md#using-arm-compiler)
 - [Configuring the build for simple_platform](../sections/building.md#configuring-the-build-for-simple_platform)
 - [Working with model debugger from Arm Fast Model Tools](../sections/building.md#working-with-model-debugger-from-arm-fast-model-tools)
-- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos-u-npu-variants)
+- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos_u-npu-variants)
 
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
diff --git a/docs/use_cases/img_class.md b/docs/use_cases/img_class.md
index 9423a4e..b3544de 100644
--- a/docs/use_cases/img_class.md
+++ b/docs/use_cases/img_class.md
@@ -100,7 +100,7 @@ For further information, please refer to:
 - [Using Arm Compiler](../sections/building.md#using-arm-compiler)
 - [Configuring the build for simple_platform](../sections/building.md#configuring-the-build-for-simple_platform)
 - [Working with model debugger from Arm Fast Model Tools](../sections/building.md#working-with-model-debugger-from-arm-fast-model-tools)
-- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos-u-npu-variants)
+- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos_u-npu-variants)
 
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
diff --git a/docs/use_cases/inference_runner.md b/docs/use_cases/inference_runner.md
index bd19840..91cca44 100644
--- a/docs/use_cases/inference_runner.md
+++ b/docs/use_cases/inference_runner.md
@@ -92,7 +92,7 @@ For further information, please refer to:
 - [Using Arm Compiler](../sections/building.md#using-arm-compiler)
 - [Configuring the build for simple_platform](../sections/building.md#configuring-the-build-for-simple_platform)
 - [Working with model debugger from Arm Fast Model Tools](../sections/building.md#working-with-model-debugger-from-arm-fast-model-tools)
-- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos-u-npu-variants)
+- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos_u-npu-variants)
 
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
diff --git a/docs/use_cases/kws.md b/docs/use_cases/kws.md
index 5839947..d6bfc3a 100644
--- a/docs/use_cases/kws.md
+++ b/docs/use_cases/kws.md
@@ -149,7 +149,7 @@ For further information, please refer to:
 - [Using Arm Compiler](../sections/building.md#using-arm-compiler)
 - [Configuring the build for simple_platform](../sections/building.md#configuring-the-build-for-simple_platform)
 - [Working with model debugger from Arm Fast Model Tools](../sections/building.md#working-with-model-debugger-from-arm-fast-model-tools)
-- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos-u-npu-variants)
+- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos_u-npu-variants)
 
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
diff --git a/docs/use_cases/kws_asr.md b/docs/use_cases/kws_asr.md
index 51d1840..8b2f123 100644
--- a/docs/use_cases/kws_asr.md
+++ b/docs/use_cases/kws_asr.md
@@ -242,7 +242,7 @@ For further information, please refer to:
 - [Using Arm Compiler](../sections/building.md#using-arm-compiler)
 - [Configuring the build for simple_platform](../sections/building.md#configuring-the-build-for-simple_platform)
 - [Working with model debugger from Arm Fast Model Tools](../sections/building.md#working-with-model-debugger-from-arm-fast-model-tools)
-- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos-u-npu-variants)
+- [Building for different Ethos-U NPU variants](../sections/building.md#building-for-different-ethos_u-npu-variants)
 
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
index 55ed5d7..dd53a57 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
@@ -18,7 +18,7 @@
 ; *************************************************************
 ; Please see docs/sections/appendix.md for memory mapping information.
 ;
-; Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
 ;       the model should only be placed in those regions.
 ;
 ;---------------------------------------------------------
@@ -63,7 +63,7 @@ LOAD_REGION_0       0x00000000                  0x00080000
     ; SSE-300's internal SRAM of 4MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
-    ; both Cortex-M55 and Ethos-U55
+    ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
     isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
     {
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
index deb4214..0c6a388 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
@@ -59,7 +59,7 @@ LOAD_REGION_0       0x00000000                  0x00080000
     ; SSE-300's internal SRAM of 4MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
-    ; both Cortex-M55 and Ethos-U55
+    ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
     isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
     {