From c30f495dc013a73e371dd8053a0381e4707ab309 Mon Sep 17 00:00:00 2001 From: Tim Hall Date: Mon, 15 Jun 2020 20:47:35 +0100 Subject: Code clean-up using black and flake8 - No functional change Signed-off-by: Tim Hall Change-Id: I5ab1198b9d092cd041fa9b85b2dee9900d299bfc --- ethosu/vela/architecture_features.py | 11 +++- ethosu/vela/graph_optimiser.py | 18 +++--- ethosu/vela/greedy_allocation.py | 4 +- ethosu/vela/high_level_command_stream.py | 12 +++- ethosu/vela/high_level_command_stream_generator.py | 68 +++++++++++++++++----- ethosu/vela/insert_dma.py | 9 +-- ethosu/vela/mark_tensors.py | 4 +- ethosu/vela/npu_performance.py | 5 +- ethosu/vela/npu_serialisation.py | 8 ++- ethosu/vela/numeric_util.py | 3 +- ethosu/vela/scheduler.py | 2 +- ethosu/vela/shared_buffer_allocation.py | 4 +- ethosu/vela/supported_operators.py | 52 ++++++++--------- ethosu/vela/tflite_mapping.py | 3 +- ethosu/vela/tflite_reader.py | 3 +- ethosu/vela/weight_compressor.py | 4 +- 16 files changed, 135 insertions(+), 75 deletions(-) (limited to 'ethosu/vela') diff --git a/ethosu/vela/architecture_features.py b/ethosu/vela/architecture_features.py index 15cf0ea4..58ab0ad3 100644 --- a/ethosu/vela/architecture_features.py +++ b/ethosu/vela/architecture_features.py @@ -342,9 +342,14 @@ Note the difference between ArchitectureFeatures and CompilerOptions return min(max_block_depth, ifm_depth) # Calculate the size of the IFM block given a depth, target OFM block and a kernel - def get_ifm_block_size(self, ifm_block_depth, ofm_block: Block, - kernel: Kernel, subkernel: Block = Block(8, 8, 65536), - ifm_resampling_mode=resampling_mode.NONE): + def get_ifm_block_size( + self, + ifm_block_depth, + ofm_block: Block, + kernel: Kernel, + subkernel: Block = Block(8, 8, 65536), + ifm_resampling_mode=resampling_mode.NONE, + ): upscaling = 1 if ifm_resampling_mode == resampling_mode.NONE else 2 # Height ifm_odd_2x_height_enable = 0 diff --git a/ethosu/vela/graph_optimiser.py b/ethosu/vela/graph_optimiser.py index 8a393a2e..cd4ac63e 100644 --- a/ethosu/vela/graph_optimiser.py +++ b/ethosu/vela/graph_optimiser.py @@ -131,6 +131,7 @@ def calc_padding_and_skirt(padding_type, kernel_size, stride, input_dims): skirt = (top_pad, left_pad, ypad - top_pad, xpad - left_pad) return padding, skirt + def calc_upscaled_padding_and_skirt(padding_type, kernel_size, stride, input_dims): upscaled_shape = [input_dims[0], input_dims[1] * stride[1], input_dims[2] * stride[2], input_dims[3]] ypad = needed_total_padding(int(upscaled_shape[1]), int(stride[1]), int(kernel_size[0])) @@ -174,7 +175,7 @@ def fixup_conv2d_backprop(op, arch): op.inputs.append(scale_tens) # Update strides - op.attrs.update( {"stride_w": 1, "stride_h": 1, "strides": (1,1,1,1)} ) + op.attrs.update({"stride_w": 1, "stride_h": 1, "strides": (1, 1, 1, 1)}) return op @@ -331,11 +332,15 @@ def add_padding_fields(op, arch): raise UnsupportedFeatureError("Unknown operation that uses padding: {}".format(op.type)) if op.type == "Conv2DBackpropInputSwitchedBias": - padding, skirt = calc_upscaled_padding_and_skirt(op.attrs["padding"], kernel_size, op.attrs["strides"], input_shape) + padding, skirt = calc_upscaled_padding_and_skirt( + op.attrs["padding"], kernel_size, op.attrs["strides"], input_shape + ) else: dilation_h, dilation_w = op.get_dilation_h_w() dilated_kernel_size = [dilation_h * (kernel_size[0] - 1) + 1, dilation_w * (kernel_size[1] - 1) + 1] - padding, skirt = calc_padding_and_skirt(op.attrs["padding"], dilated_kernel_size, op.attrs["strides"], input_shape) + padding, skirt = calc_padding_and_skirt( + op.attrs["padding"], dilated_kernel_size, op.attrs["strides"], input_shape + ) op.attrs["explicit_padding"] = padding op.attrs["skirt"] = skirt @@ -540,7 +545,7 @@ def convert_mul_max_to_abs_or_lrelu(op, arch): def add_attrs_to_resizebilinear(op, arch): - if op.type == 'ResizeBilinear' and op.run_on_npu: + if op.type == "ResizeBilinear" and op.run_on_npu: input_tensor = op.inputs[0] upscaled_shape = [input_tensor.shape[1] * 2, input_tensor.shape[2] * 2] out_shape = op.outputs[0].shape[1:3] @@ -556,10 +561,7 @@ def add_attrs_to_resizebilinear(op, arch): # If this exception is raised, something is wrong with the supported op check raise UnsupportedFeatureError("Unsupported upscaling factor") input_tensor.resampling_mode = resampling_mode.NEAREST - op.attrs.update({ - 'strides': (1, 1, 1, 1), - 'ksize': (1, 2, 2, 1), - }) + op.attrs.update({"strides": (1, 1, 1, 1), "ksize": (1, 2, 2, 1)}) return op diff --git a/ethosu/vela/greedy_allocation.py b/ethosu/vela/greedy_allocation.py index 8393434d..e0176875 100644 --- a/ethosu/vela/greedy_allocation.py +++ b/ethosu/vela/greedy_allocation.py @@ -77,7 +77,9 @@ class GreedyAllocator: for m in lrs: if n != m and n.overlaps_ranges(m): overlap, tens_n, tens_m = n.overlaps_address(m) - if overlap and not (tens_n.equivalence_id == tens_m.equivalence_id and tens_n.address == tens_m.address): + if overlap and not ( + tens_n.equivalence_id == tens_m.equivalence_id and tens_n.address == tens_m.address + ): print("Solution failed, overlapping buffer!") print(tens_n.address, tens_n.address + n.size, n.name) print(tens_m.address, tens_m.address + m.size, m.name) diff --git a/ethosu/vela/high_level_command_stream.py b/ethosu/vela/high_level_command_stream.py index f9048a1e..be8aac8c 100644 --- a/ethosu/vela/high_level_command_stream.py +++ b/ethosu/vela/high_level_command_stream.py @@ -34,8 +34,16 @@ class Box: assert self.start_coord[i] <= self.end_coord[i] def transform_with_strides_and_skirt( - self, strides, skirt, ifm_shape, npu_block_type, concat_axis=0, concat_offset=0, split_offset=None, k_height=1, - upscaling_factor=1 + self, + strides, + skirt, + ifm_shape, + npu_block_type, + concat_axis=0, + concat_offset=0, + split_offset=None, + k_height=1, + upscaling_factor=1, ): new_start_coord = list(self.start_coord) new_end_coord = list(self.end_coord) diff --git a/ethosu/vela/high_level_command_stream_generator.py b/ethosu/vela/high_level_command_stream_generator.py index ab72fbcd..d02fd85d 100644 --- a/ethosu/vela/high_level_command_stream_generator.py +++ b/ethosu/vela/high_level_command_stream_generator.py @@ -33,14 +33,13 @@ def dma_if_necessary(ps, box, tensor): in_tensor = dma_op.inputs[0] yield DMA(in_tensor, tensor, box) + def match_tensor(source, derived): if source == derived: return True ops = derived.ops - return (ops != [] and - len(ops) ==1 and - ops[0].type == "SplitSliceRead" and - source == ops[0].inputs[0]) + return ops != [] and len(ops) == 1 and ops[0].type == "SplitSliceRead" and source == ops[0].inputs[0] + def generate_high_level_command_stream_for_pass(strat, passes, block_configs, idx): is_first = idx == 0 @@ -59,8 +58,7 @@ def generate_high_level_command_stream_for_pass(strat, passes, block_configs, id if len(ps.inputs) == 2 and npu_block_type == NpuBlockType.ElementWise: # Ensure correct imf and ifm2 order - if (match_tensor(ps.inputs[0], ps.primary_op.inputs[1]) and - match_tensor(ps.inputs[1], ps.primary_op.inputs[0])): + if match_tensor(ps.inputs[0], ps.primary_op.inputs[1]) and match_tensor(ps.inputs[1], ps.primary_op.inputs[0]): ps.ifm_tensor, ps.ifm2_tensor = ps.ifm2_tensor, ps.ifm_tensor split_offsets[0], split_offsets[1] = split_offsets[1], split_offsets[0] @@ -117,21 +115,46 @@ def generate_high_level_command_stream_for_pass(strat, passes, block_configs, id if ifm_tensor.shape != []: ifm_box, _, _ = ofm_box.transform_with_strides_and_skirt( - strides, skirt, ifm_tensor.shape, npu_block_type, concat_axis, concat_offset, split_offsets[0], upscaling + strides, + skirt, + ifm_tensor.shape, + npu_block_type, + concat_axis, + concat_offset, + split_offsets[0], + upscaling, ) else: ifm_box = Box([], []) if ifm2_tensor is not None and ifm2_tensor.shape != []: ifm2_box, _, _ = ofm_box.transform_with_strides_and_skirt( - strides, skirt, ifm2_tensor.shape, npu_block_type, concat_axis, concat_offset, split_offsets[1], upscaling + strides, + skirt, + ifm2_tensor.shape, + npu_block_type, + concat_axis, + concat_offset, + split_offsets[1], + upscaling, ) else: ifm2_box = Box([], []) for intermediate in ps.intermediates: - if intermediate != None and intermediate.shape != [] and intermediate.purpose == TensorPurpose.FeatureMap: + if ( + intermediate is not None + and intermediate.shape != [] + and intermediate.purpose == TensorPurpose.FeatureMap + ): intermediate_box, _, _ = ofm_box.transform_with_strides_and_skirt( - strides, skirt, intermediate.shape, npu_block_type, concat_axis, concat_offset, split_offsets[0], upscaling + strides, + skirt, + intermediate.shape, + npu_block_type, + concat_axis, + concat_offset, + split_offsets[0], + upscaling, ) yield from dma_if_necessary(ps, intermediate_box, intermediate) @@ -218,13 +241,32 @@ def generate_high_level_command_stream_for_pass(strat, passes, block_configs, id k_height = weight_tensor.shape[0] ifm_box, pad_top, pad_bottom = ofm_box.transform_with_strides_and_skirt( - strides, skirt, ifm_tensor.shape, npu_block_type, concat_axis, concat_offset, split_offsets[0], k_height, upscaling + strides, + skirt, + ifm_tensor.shape, + npu_block_type, + concat_axis, + concat_offset, + split_offsets[0], + k_height, + upscaling, ) for intermediate in ps.intermediates: - if intermediate != None and intermediate.shape != [] and intermediate.purpose == TensorPurpose.FeatureMap: + if ( + intermediate is not None + and intermediate.shape != [] + and intermediate.purpose == TensorPurpose.FeatureMap + ): intermediate_box, _, _ = ofm_box.transform_with_strides_and_skirt( - strides, skirt, intermediate.shape, npu_block_type, concat_axis, concat_offset, split_offsets[0], upscaling + strides, + skirt, + intermediate.shape, + npu_block_type, + concat_axis, + concat_offset, + split_offsets[0], + upscaling, ) yield from dma_if_necessary(ps, intermediate_box, intermediate) diff --git a/ethosu/vela/insert_dma.py b/ethosu/vela/insert_dma.py index eef42bf6..7049a05f 100644 --- a/ethosu/vela/insert_dma.py +++ b/ethosu/vela/insert_dma.py @@ -21,18 +21,19 @@ from .operation import Operation from .tensor import MemArea from .tensor import TensorPurpose + binary_elementwise_op = set(("AddAct", "MulAct", "SubAct", "Maximum", "Minimum")) + def insert_dma_cmd(op, arch): if op.type == "DMA": return op # Already rewritten for idx, tens in enumerate(op.inputs): if tens.mem_area in (MemArea.Dram, MemArea.OffChipFlash) and tens.mem_area != arch.fast_storage_mem_area: - if (tens.purpose == TensorPurpose.Weights or - (tens.purpose == TensorPurpose.FeatureMap and - op.type in binary_elementwise_op and - tens.shape != [])): + if tens.purpose == TensorPurpose.Weights or ( + tens.purpose == TensorPurpose.FeatureMap and op.type in binary_elementwise_op and tens.shape != [] + ): only_vector_product_consumers = True for oper in tens.consumers(): if oper is None or oper.attrs.get("npu_block_type") != NpuBlockType.VectorProduct: diff --git a/ethosu/vela/mark_tensors.py b/ethosu/vela/mark_tensors.py index b557f903..72ab8cfa 100644 --- a/ethosu/vela/mark_tensors.py +++ b/ethosu/vela/mark_tensors.py @@ -112,7 +112,9 @@ tensor_purposes = [ # ops, input_purpose ), ( set(("Conv2DBackpropInputSwitchedBias",)), - purpose_from_list([TensorPurpose.FeatureMap, TensorPurpose.Weights, TensorPurpose.FeatureMap, TensorPurpose.FeatureMap]), + purpose_from_list( + [TensorPurpose.FeatureMap, TensorPurpose.Weights, TensorPurpose.FeatureMap, TensorPurpose.FeatureMap] + ), ), ( set(("QuantizedConv2D", "QuantizedMatMul")), diff --git a/ethosu/vela/npu_performance.py b/ethosu/vela/npu_performance.py index abe7134d..98626de6 100644 --- a/ethosu/vela/npu_performance.py +++ b/ethosu/vela/npu_performance.py @@ -25,7 +25,6 @@ import numpy as np from . import numeric_util from .architecture_features import Block -from .architecture_features import Kernel from .nn_graph import PassPlacement from .nn_graph import SchedulerRewrite from .operation import NpuBlockType @@ -241,7 +240,9 @@ def performance_metrics_for_pass(arch, ps, block_config=None, rewrite_list=[], f ifm_tensor, _, weight_tensor, ofm_tensor = ps.get_primary_op_ifm_ifm2_weights_ofm() - if npu_block_type in set((NpuBlockType.ConvolutionMxN, NpuBlockType.ConvolutionDepthWise, NpuBlockType.Pooling)): + if npu_block_type in set( + (NpuBlockType.ConvolutionMxN, NpuBlockType.ConvolutionDepthWise, NpuBlockType.Pooling) + ): # extent the ifm to full dimension ifm_tensor_brick_size = tuple(numeric_util.full_shape(4, list(ifm_tensor.brick_size), 1)) ifm_tensor_shape = numeric_util.full_shape(4, ifm_tensor.shape, 1) diff --git a/ethosu/vela/npu_serialisation.py b/ethosu/vela/npu_serialisation.py index 0cb40ed0..08dc0d38 100644 --- a/ethosu/vela/npu_serialisation.py +++ b/ethosu/vela/npu_serialisation.py @@ -46,11 +46,13 @@ def copy_compressed_values_to_memory_tensor(memory_tensor, src_tensor): memory_tensor.values[start_addr:end_addr] = compressed_values start_addr = end_addr + def copy_ifm_values_to_memory_tensor(memory_tensor, src_tensor): start_addr = src_tensor.address end_addr = start_addr + src_tensor.quant_values.size memory_tensor.values[start_addr:end_addr] = src_tensor.quant_values + def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, flash_tens): if sg.placement != PassPlacement.Npu: return scratch_tens, flash_tens @@ -95,7 +97,7 @@ def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, flash_tens) for cps in sg.cascaded_passes: for ps in cps.passes: if ps.placement == PassPlacement.Npu: - if ps.weight_tensor != None: + if ps.weight_tensor is not None: # For DMA ops, ps.weight_tensor is referring to the SRAM weight tensor and therefore the address # is pointing at the destination address of where the weights should be placed in SRAM. # This ensures that the Flash weight tensor is used instead and thus gets the correct address. @@ -106,9 +108,9 @@ def serialise_npu_subgraph_into_tensors(nng, sg, arch, scratch_tens, flash_tens) copy_compressed_values_to_memory_tensor(sg.flash_tensor, ps.scale_tensor) - if ps.ifm_tensor != None and ps.ifm_tensor.mem_area != MemArea.Sram: + if ps.ifm_tensor is not None and ps.ifm_tensor.mem_area != MemArea.Sram: copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.ifm_tensor) - if ps.ifm2_tensor != None and ps.ifm2_tensor.mem_area != MemArea.Sram: + if ps.ifm2_tensor is not None and ps.ifm2_tensor.mem_area != MemArea.Sram: copy_ifm_values_to_memory_tensor(sg.flash_tensor, ps.ifm2_tensor) sg.command_stream_tensor = make_memory_tensor( diff --git a/ethosu/vela/numeric_util.py b/ethosu/vela/numeric_util.py index 9adf5ecb..70209fba 100644 --- a/ethosu/vela/numeric_util.py +++ b/ethosu/vela/numeric_util.py @@ -86,5 +86,6 @@ def clamp_sigmoid(x): y = 1 / (1 + math.exp(-x)) return y + def full_shape(dim, shape, fill): - return ([fill] * (dim - len(shape))) + shape \ No newline at end of file + return ([fill] * (dim - len(shape))) + shape diff --git a/ethosu/vela/scheduler.py b/ethosu/vela/scheduler.py index e45e3e55..0b594310 100644 --- a/ethosu/vela/scheduler.py +++ b/ethosu/vela/scheduler.py @@ -940,7 +940,7 @@ class DynamicProgrammingScheduler: use_NHCWB16 = True for op in output.consumer_list: - if op == None or op.type == 'Reshape': + if op is None or op.type == "Reshape": use_NHCWB16 = False else: use_NHCWB16 &= op.run_on_npu diff --git a/ethosu/vela/shared_buffer_allocation.py b/ethosu/vela/shared_buffer_allocation.py index 72caa1b6..040f2a3b 100644 --- a/ethosu/vela/shared_buffer_allocation.py +++ b/ethosu/vela/shared_buffer_allocation.py @@ -106,7 +106,9 @@ class SharedBufferAllocation: def try_block(self, ofm_block: Block): # Get IFM block configuration ifm_block_depth = ofm_block.depth if self.is_equal_depth_op else self.ifm_block_depth - ifm_block = self.arch.get_ifm_block_size(ifm_block_depth, ofm_block, self.kernel, ifm_resampling_mode=self.ifm_resampling_mode) + ifm_block = self.arch.get_ifm_block_size( + ifm_block_depth, ofm_block, self.kernel, ifm_resampling_mode=self.ifm_resampling_mode + ) ifm_config = self.arch.get_block_config(ifm_block.width, ifm_block.height, ifm_block.depth) if ifm_config is None: return None diff --git a/ethosu/vela/supported_operators.py b/ethosu/vela/supported_operators.py index 5676ba1c..55e718e9 100644 --- a/ethosu/vela/supported_operators.py +++ b/ethosu/vela/supported_operators.py @@ -15,7 +15,8 @@ # limitations under the License. # Description: # The SupportedOperators class which is a collection of all supported operators and parameter checks. -from .data_type import BaseType, DataType +from .data_type import BaseType +from .data_type import DataType class SupportedOperators: @@ -51,17 +52,7 @@ class SupportedOperators: self.unary_elem_wise_main_ops = set(("LeakyRelu", "Abs")) self.binary_elem_wise_min_max_ops = set(("Minimum", "Maximum")) self.binary_elem_wise_add_mul_sub = set( - ( - "AddAct", - "MulAct", - "SubAct", - "QuantizedAdd", - "QuantizedSub", - "QuantizedMul", - "Mul", - "Add", - "Sub", - ) + ("AddAct", "MulAct", "SubAct", "QuantizedAdd", "QuantizedSub", "QuantizedMul", "Mul", "Add", "Sub",) ) self.binary_elem_wise_main_ops = self.binary_elem_wise_min_max_ops | self.binary_elem_wise_add_mul_sub self.elem_wise_main_ops = self.binary_elem_wise_main_ops | self.unary_elem_wise_main_ops @@ -201,13 +192,13 @@ class SupportedOperators: return False elif op.attrs["padding"] == b"VALID": kernel_h, kernel_w = weight_tensor.shape[0], weight_tensor.shape[1] - if ((ofm_h != (ifm_h) * stride_h + max(kernel_h - stride_h, 0)) - or (ofm_w != (ifm_w) * stride_w + max(kernel_w - stride_w, 0))): + if (ofm_h != (ifm_h) * stride_h + max(kernel_h - stride_h, 0)) or ( + ofm_w != (ifm_w) * stride_w + max(kernel_w - stride_w, 0) + ): return False return self.check_convolution_restrictions(op) - def check_pooling_restrictions(self, op): # check stride if op.attrs["stride_w"] > 3 or op.attrs["stride_h"] > 3: @@ -226,8 +217,9 @@ class SupportedOperators: # check kernel size if op.attrs["padding"] == b"SAME" and (op.attrs["filter_width"] > 8 or op.attrs["filter_height"] > 8): return False - if (op.attrs["padding"] == b"VALID" and - (op.attrs["filter_width"] * op.attrs["filter_height"] > 256 * 256 or op.attrs["filter_height"] > 256)): + if op.attrs["padding"] == b"VALID" and ( + op.attrs["filter_width"] * op.attrs["filter_height"] > 256 * 256 or op.attrs["filter_height"] > 256 + ): return False if op.type in self.max_pooling_ops: @@ -259,31 +251,33 @@ class SupportedOperators: # check data type ifm_tensor, ifm2_tensor, _, ofm_tensor = op.get_ifm_ifm2_weights_ofm() # input and output datatype must match for these operators - if (op.type in self.binary_elem_wise_min_max_ops | self.unary_elem_wise_main_ops and - ifm_tensor.dtype != ofm_tensor.dtype): + if ( + op.type in self.binary_elem_wise_min_max_ops | self.unary_elem_wise_main_ops + and ifm_tensor.dtype != ofm_tensor.dtype + ): return False - if (op.type in self.binary_elem_wise_add_mul_sub): + if op.type in self.binary_elem_wise_add_mul_sub: # both inputs must have same type - if (ifm_tensor.dtype != ifm2_tensor.dtype): + if ifm_tensor.dtype != ifm2_tensor.dtype: return False # signed input check - if (ifm_tensor.dtype.type & BaseType.Signed): + if ifm_tensor.dtype.type & BaseType.Signed: # output must be signed - if (ofm_tensor.dtype.type & BaseType.Unsigned): + if ofm_tensor.dtype.type & BaseType.Unsigned: return False # and 8, 16 or 32-bit - if (ofm_tensor.element_size() not in (1, 2, 4)): + if ofm_tensor.element_size() not in (1, 2, 4): return False # unsigned input check, output must be same type or int32 - if (ifm_tensor.dtype.type & BaseType.Unsigned and not - (ifm_tensor.dtype == ofm_tensor.dtype or - ofm_tensor.dtype == DataType.int32)): + if ifm_tensor.dtype.type & BaseType.Unsigned and not ( + ifm_tensor.dtype == ofm_tensor.dtype or ofm_tensor.dtype == DataType.int32 + ): return False # check batch size if len(ifm_tensor.shape) > 2 and ifm_tensor.shape[0] != 1: - return False - if op.type in self.binary_elem_wise_main_ops: # if op type is unary, ifm2_tensor is None + return False + if op.type in self.binary_elem_wise_main_ops: # if op type is unary, ifm2_tensor is None if len(ifm2_tensor.shape) > 2 and ifm2_tensor.shape[0] != 1: return False diff --git a/ethosu/vela/tflite_mapping.py b/ethosu/vela/tflite_mapping.py index 06097cd0..d077768c 100644 --- a/ethosu/vela/tflite_mapping.py +++ b/ethosu/vela/tflite_mapping.py @@ -260,7 +260,6 @@ builtin_options_map = { BuiltinOptions.DensifyOptions: DensifyOptions.DensifyOptions, BuiltinOptions.DepthToSpaceOptions: DepthToSpaceOptions.DepthToSpaceOptions, BuiltinOptions.HardSwishOptions: HardSwishOptions.HardSwishOptions, - BuiltinOptions.IfOptions: IfOptions.IfOptions, BuiltinOptions.NonMaxSuppressionV4Options: NonMaxSuppressionV4Options.NonMaxSuppressionV4Options, BuiltinOptions.NonMaxSuppressionV5Options: NonMaxSuppressionV5Options.NonMaxSuppressionV5Options, @@ -536,7 +535,7 @@ builtin_operator_map = { ), ), ), - BuiltinOperator.PRELU : ("Prelu", None), + BuiltinOperator.PRELU: ("Prelu", None), BuiltinOperator.MAXIMUM: ("Maximum", OptionsSerializer("MaximumMinimumOptions")), BuiltinOperator.ARG_MAX: ( "ArgMax", diff --git a/ethosu/vela/tflite_reader.py b/ethosu/vela/tflite_reader.py index 84c4c3c2..5667aff5 100644 --- a/ethosu/vela/tflite_reader.py +++ b/ethosu/vela/tflite_reader.py @@ -20,7 +20,6 @@ import os.path import numpy as np from .errors import InputFileError -from .errors import UnsupportedFeatureError from .nn_graph import Graph from .nn_graph import Subgraph from .operation import Operation @@ -229,7 +228,7 @@ class TFLiteGraph: def parse_operator_code(self, code): c = code.BuiltinCode() - if not c in builtin_operator_map: + if c not in builtin_operator_map: msg = "The input file contains operator code {} which is currently not supported".format(c) raise InputFileError(self.name, msg) op_type, ser = builtin_operator_map[c] diff --git a/ethosu/vela/weight_compressor.py b/ethosu/vela/weight_compressor.py index df2b0573..c5f4ce10 100644 --- a/ethosu/vela/weight_compressor.py +++ b/ethosu/vela/weight_compressor.py @@ -19,6 +19,7 @@ import math from collections import namedtuple import numpy as np +from ethosu import mlw_codec from .data_type import DataType from .errors import UnsupportedFeatureError @@ -31,7 +32,6 @@ from .tensor import TensorBlockTraversal from .tensor import TensorFormat from .tensor import TensorPurpose from .tensor import TensorSubPurpose -from ethosu import mlw_codec # Contains meta info for a weight compression. If two tensors have identical weight compression config, @@ -236,7 +236,7 @@ def compress_weights(arch, nng, tens, npu_block_type, ofm_block_depth, ofm_depth if tens.consumer_list[0].type == "Conv2DBackpropInputSwitchedBias": # Transpose Convoluion, reverse weights in H and W axes - weights = np.flip(weights, axis=(0,1)) + weights = np.flip(weights, axis=(0, 1)) # Slice weight stream up depth-ways into bricks and compress full_ofm_depth = quant_buf.shape[-1] -- cgit v1.2.1