From 77f839691cac9ff1678bd05228c7221e7ed6e9c3 Mon Sep 17 00:00:00 2001 From: Douglas Troha Date: Thu, 14 May 2020 16:36:17 +0200 Subject: Include 0.180 in HI 1.0 * Rename debug_addr to debug_address and update page names Change-Id: Ib8d84e6371437439038db411d2f8ff114590878a Signed-off-by: Douglas Troha --- ethosu/vela/ethos_u55_regs/ethos_u55_regs.py | 1488 +++++++++++++------------- 1 file changed, 744 insertions(+), 744 deletions(-) (limited to 'ethosu/vela') diff --git a/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py b/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py index 004c1ba0..058a418d 100644 --- a/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py +++ b/ethosu/vela/ethos_u55_regs/ethos_u55_regs.py @@ -22,7 +22,96 @@ from enum import Enum ARCH_VER = '1.0.0' -class DEBUG_INTERNAL(Enum): +class BASE(Enum): + ID = 0x0000 + STATUS = 0x0004 + CMD = 0x0008 + RESET = 0x000C + QBASE0 = 0x0010 + QBASE1 = 0x0014 + QREAD = 0x0018 + QCONFIG = 0x001C + QSIZE = 0x0020 + PROT = 0x0024 + CONFIG = 0x0028 + LOCK = 0x002C + REGIONCFG = 0x003C + AXI_LIMIT0 = 0x0040 + AXI_LIMIT1 = 0x0044 + AXI_LIMIT2 = 0x0048 + AXI_LIMIT3 = 0x004C + SIZE = 0x0050 + +class BASE_POINTERS(Enum): + BASEP0 = 0x0080 + BASEP1 = 0x0084 + BASEP2 = 0x0088 + BASEP3 = 0x008C + BASEP4 = 0x0090 + BASEP5 = 0x0094 + BASEP6 = 0x0098 + BASEP7 = 0x009C + BASEP8 = 0x00A0 + BASEP9 = 0x00A4 + BASEP10 = 0x00A8 + BASEP11 = 0x00AC + BASEP12 = 0x00B0 + BASEP13 = 0x00B4 + BASEP14 = 0x00B8 + BASEP15 = 0x00BC + SIZE = 0x00C0 + +class DEBUG(Enum): + WD_STATUS = 0x0100 + MAC_STATUS = 0x0104 + AO_STATUS = 0x0108 + DMA_STATUS0 = 0x0110 + DMA_STATUS1 = 0x0114 + CLKFORCE = 0x0140 + DEBUG_ADDRESS = 0x0144 + DEBUG_MISC = 0x0148 + DEBUGCORE = 0x014C + SIZE = 0x0150 + +class ID(Enum): + REVISION = 0x0FC0 + PID4 = 0x0FD0 + PID5 = 0x0FD4 + PID6 = 0x0FD8 + PID7 = 0x0FDC + PID0 = 0x0FE0 + PID1 = 0x0FE4 + PID2 = 0x0FE8 + PID3 = 0x0FEC + CID0 = 0x0FF0 + CID1 = 0x0FF4 + CID2 = 0x0FF8 + CID3 = 0x0FFC + SIZE = 0x1000 + +class PMU(Enum): + PMCR = 0x0180 + PMCNTENSET = 0x0184 + PMCNTENCLR = 0x0188 + PMOVSSET = 0x018C + PMOVSCLR = 0x0190 + PMINTSET = 0x0194 + PMINTCLR = 0x0198 + PMCCNTR_LO = 0x01A0 + PMCCNTR_HI = 0x01A4 + PMCCNTR_CFG = 0x01A8 + PMCAXI_CHAN = 0x01AC + PMEVCNTR0 = 0x0300 + PMEVCNTR1 = 0x0304 + PMEVCNTR2 = 0x0308 + PMEVCNTR3 = 0x030C + PMEVTYPER0 = 0x0380 + PMEVTYPER1 = 0x0384 + PMEVTYPER2 = 0x0388 + PMEVTYPER3 = 0x038C + SIZE = 0x0390 + +class SHARED_BUFFER(Enum): SHARED_BUFFER0 = 0x0400 SHARED_BUFFER1 = 0x0404 SHARED_BUFFER2 = 0x0408 @@ -281,96 +370,7 @@ class DEBUG_INTERNAL(Enum): SHARED_BUFFER255 = 0x07FC SIZE = 0x0800 -class HW_DEBUG_INTERNAL(Enum): - WD_STATUS = 0x0100 - MAC_STATUS = 0x0104 - AO_STATUS = 0x0108 - DMA_STATUS0 = 0x0110 - DMA_STATUS1 = 0x0114 - CLKFORCE = 0x0140 - DEBUG_ADDR = 0x0144 - DEBUG_MISC = 0x0148 - DEBUGCORE = 0x014C - SIZE = 0x0150 - -class NPU_BP(Enum): - BASEP0 = 0x0080 - BASEP1 = 0x0084 - BASEP2 = 0x0088 - BASEP3 = 0x008C - BASEP4 = 0x0090 - BASEP5 = 0x0094 - BASEP6 = 0x0098 - BASEP7 = 0x009C - BASEP8 = 0x00A0 - BASEP9 = 0x00A4 - BASEP10 = 0x00A8 - BASEP11 = 0x00AC - BASEP12 = 0x00B0 - BASEP13 = 0x00B4 - BASEP14 = 0x00B8 - BASEP15 = 0x00BC - SIZE = 0x00C0 - -class NPU_IDS(Enum): - REVISION = 0x0FC0 - PID4 = 0x0FD0 - PID5 = 0x0FD4 - PID6 = 0x0FD8 - PID7 = 0x0FDC - PID0 = 0x0FE0 - PID1 = 0x0FE4 - PID2 = 0x0FE8 - PID3 = 0x0FEC - CID0 = 0x0FF0 - CID1 = 0x0FF4 - CID2 = 0x0FF8 - CID3 = 0x0FFC - SIZE = 0x1000 - -class NPU_REG(Enum): - ID = 0x0000 - STATUS = 0x0004 - CMD = 0x0008 - RESET = 0x000C - QBASE0 = 0x0010 - QBASE1 = 0x0014 - QREAD = 0x0018 - QCONFIG = 0x001C - QSIZE = 0x0020 - PROT = 0x0024 - CONFIG = 0x0028 - LOCK = 0x002C - REGIONCFG = 0x003C - AXI_LIMIT0 = 0x0040 - AXI_LIMIT1 = 0x0044 - AXI_LIMIT2 = 0x0048 - AXI_LIMIT3 = 0x004C - SIZE = 0x0050 - -class PMU(Enum): - PMCR = 0x0180 - PMCNTENSET = 0x0184 - PMCNTENCLR = 0x0188 - PMOVSSET = 0x018C - PMOVSCLR = 0x0190 - PMINTSET = 0x0194 - PMINTCLR = 0x0198 - PMCCNTR_LO = 0x01A0 - PMCCNTR_HI = 0x01A4 - PMCCNTR_CFG = 0x01A8 - PMCAXI_CHAN = 0x01AC - PMEVCNTR0 = 0x0300 - PMEVCNTR1 = 0x0304 - PMEVCNTR2 = 0x0308 - PMEVCNTR3 = 0x030C - PMEVTYPER0 = 0x0380 - PMEVTYPER1 = 0x0384 - PMEVTYPER2 = 0x0388 - PMEVTYPER3 = 0x038C - SIZE = 0x0390 - -class TSU_DEBUG_INTERNAL(Enum): +class TSU(Enum): IFM_PAD_TOP = 0x0800 IFM_PAD_LEFT = 0x0804 IFM_PAD_RIGHT = 0x0808 @@ -492,7 +492,7 @@ class TSU_DEBUG_INTERNAL(Enum): SCALE1_LENGTH = 0x0B58 SIZE = 0x0B5C -class TSU_DEBUG_RO_INTERNAL(Enum): +class TSU_DEBUG(Enum): KERNEL_X = 0x0200 KERNEL_Y = 0x0204 KERNEL_W_M1 = 0x0208 @@ -808,353 +808,340 @@ class stride_mode(Enum): STRIDE_MODE_3D = 2 -class wd_status_r(Union): +class id_r(Union): class _bitfield(Structure): _fields_ = [ - ("core_slice_state", c_uint32, 2), - ("core_idle", c_uint32, 1), - ("ctrl_state", c_uint32, 2), - ("ctrl_idle", c_uint32, 1), - ("write_buf_index0", c_uint32, 3), - ("write_buf_valid0", c_uint32, 1), - ("write_buf_idle0", c_uint32, 1), - ("write_buf_index1", c_uint32, 3), - ("write_buf_valid1", c_uint32, 1), - ("write_buf_idle1", c_uint32, 1), - ("events", c_uint32, 12), - ("reserved0", c_uint32, 4), + ("version_status", c_uint32, 4), + ("version_minor", c_uint32, 4), + ("version_major", c_uint32, 4), + ("product_major", c_uint32, 4), + ("arch_patch_rev", c_uint32, 4), + ("arch_minor_rev", c_uint32, 8), + ("arch_major_rev", c_uint32, 4), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_core_slice_state(self, value): self.bits.core_slice_state = value - def get_core_slice_state(self): value = self.bits.core_slice_state; return value - def set_core_idle(self, value): self.bits.core_idle = value - def get_core_idle(self): value = self.bits.core_idle; return value - def set_ctrl_state(self, value): self.bits.ctrl_state = value - def get_ctrl_state(self): value = self.bits.ctrl_state; return value - def set_ctrl_idle(self, value): self.bits.ctrl_idle = value - def get_ctrl_idle(self): value = self.bits.ctrl_idle; return value - def set_write_buf_index0(self, value): self.bits.write_buf_index0 = value - def get_write_buf_index0(self): value = self.bits.write_buf_index0; return value - def set_write_buf_valid0(self, value): self.bits.write_buf_valid0 = value - def get_write_buf_valid0(self): value = self.bits.write_buf_valid0; return value - def set_write_buf_idle0(self, value): self.bits.write_buf_idle0 = value - def get_write_buf_idle0(self): value = self.bits.write_buf_idle0; return value - def set_write_buf_index1(self, value): self.bits.write_buf_index1 = value - def get_write_buf_index1(self): value = self.bits.write_buf_index1; return value - def set_write_buf_valid1(self, value): self.bits.write_buf_valid1 = value - def get_write_buf_valid1(self): value = self.bits.write_buf_valid1; return value - def set_write_buf_idle1(self, value): self.bits.write_buf_idle1 = value - def get_write_buf_idle1(self): value = self.bits.write_buf_idle1; return value - def set_events(self, value): self.bits.events = value - def get_events(self): value = self.bits.events; return value + def set_version_status(self, value): self.bits.version_status = value + def get_version_status(self): value = self.bits.version_status; return value + def set_version_minor(self, value): self.bits.version_minor = value + def get_version_minor(self): value = self.bits.version_minor; return value + def set_version_major(self, value): self.bits.version_major = value + def get_version_major(self): value = self.bits.version_major; return value + def set_product_major(self, value): self.bits.product_major = value + def get_product_major(self): value = self.bits.product_major; return value + def set_arch_patch_rev(self, value): self.bits.arch_patch_rev = value + def get_arch_patch_rev(self): value = self.bits.arch_patch_rev; return value + def set_arch_minor_rev(self, value): self.bits.arch_minor_rev = value + def get_arch_minor_rev(self): value = self.bits.arch_minor_rev; return value + def set_arch_major_rev(self, value): self.bits.arch_major_rev = value + def get_arch_major_rev(self): value = self.bits.arch_major_rev; return value -class mac_status_r(Union): +class status_r(Union): class _bitfield(Structure): _fields_ = [ - ("block_cfg_valid", c_uint32, 1), - ("trav_en", c_uint32, 1), - ("wait_for_ib", c_uint32, 1), - ("wait_for_acc_buf", c_uint32, 1), - ("wait_for_weights", c_uint32, 1), - ("stall_stripe", c_uint32, 1), - ("dw_sel", c_uint32, 1), - ("wait_for_dw0_ready", c_uint32, 1), - ("wait_for_dw1_ready", c_uint32, 1), - ("acc_buf_sel_ai", c_uint32, 1), - ("wait_for_acc0_ready", c_uint32, 1), - ("wait_for_acc1_ready", c_uint32, 1), - ("acc_buf_sel_aa", c_uint32, 1), - ("acc0_valid", c_uint32, 1), - ("acc1_valid", c_uint32, 1), - ("reserved0", c_uint32, 1), - ("events", c_uint32, 11), - ("reserved1", c_uint32, 5), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_block_cfg_valid(self, value): self.bits.block_cfg_valid = value - def get_block_cfg_valid(self): value = self.bits.block_cfg_valid; return value - def set_trav_en(self, value): self.bits.trav_en = value - def get_trav_en(self): value = self.bits.trav_en; return value - def set_wait_for_ib(self, value): self.bits.wait_for_ib = value - def get_wait_for_ib(self): value = self.bits.wait_for_ib; return value - def set_wait_for_acc_buf(self, value): self.bits.wait_for_acc_buf = value - def get_wait_for_acc_buf(self): value = self.bits.wait_for_acc_buf; return value - def set_wait_for_weights(self, value): self.bits.wait_for_weights = value - def get_wait_for_weights(self): value = self.bits.wait_for_weights; return value - def set_stall_stripe(self, value): self.bits.stall_stripe = value - def get_stall_stripe(self): value = self.bits.stall_stripe; return value - def set_dw_sel(self, value): self.bits.dw_sel = value - def get_dw_sel(self): value = self.bits.dw_sel; return value - def set_wait_for_dw0_ready(self, value): self.bits.wait_for_dw0_ready = value - def get_wait_for_dw0_ready(self): value = self.bits.wait_for_dw0_ready; return value - def set_wait_for_dw1_ready(self, value): self.bits.wait_for_dw1_ready = value - def get_wait_for_dw1_ready(self): value = self.bits.wait_for_dw1_ready; return value - def set_acc_buf_sel_ai(self, value): self.bits.acc_buf_sel_ai = value - def get_acc_buf_sel_ai(self): value = self.bits.acc_buf_sel_ai; return value - def set_wait_for_acc0_ready(self, value): self.bits.wait_for_acc0_ready = value - def get_wait_for_acc0_ready(self): value = self.bits.wait_for_acc0_ready; return value - def set_wait_for_acc1_ready(self, value): self.bits.wait_for_acc1_ready = value - def get_wait_for_acc1_ready(self): value = self.bits.wait_for_acc1_ready; return value - def set_acc_buf_sel_aa(self, value): self.bits.acc_buf_sel_aa = value - def get_acc_buf_sel_aa(self): value = self.bits.acc_buf_sel_aa; return value - def set_acc0_valid(self, value): self.bits.acc0_valid = value - def get_acc0_valid(self): value = self.bits.acc0_valid; return value - def set_acc1_valid(self, value): self.bits.acc1_valid = value - def get_acc1_valid(self): value = self.bits.acc1_valid; return value - def set_events(self, value): self.bits.events = value - def get_events(self): value = self.bits.events; return value + ("state", c_uint32, 1), + ("irq_raised", c_uint32, 1), + ("bus_status", c_uint32, 1), + ("reset_status", c_uint32, 1), + ("cmd_parse_error", c_uint32, 1), + ("cmd_end_reached", c_uint32, 1), + ("pmu_irq_raised", c_uint32, 1), + ("wd_fault", c_uint32, 1), + ("reserved0", c_uint32, 3), + ("faulting_interface", c_uint32, 1), + ("faulting_channel", c_uint32, 4), + ("irq_history_mask", c_uint32, 16), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_state(self, value): self.bits.state = value + def get_state(self): value = self.bits.state; return value + def set_irq_raised(self, value): self.bits.irq_raised = value + def get_irq_raised(self): value = self.bits.irq_raised; return value + def set_bus_status(self, value): self.bits.bus_status = value + def get_bus_status(self): value = self.bits.bus_status; return value + def set_reset_status(self, value): self.bits.reset_status = value + def get_reset_status(self): value = self.bits.reset_status; return value + def set_cmd_parse_error(self, value): self.bits.cmd_parse_error = value + def get_cmd_parse_error(self): value = self.bits.cmd_parse_error; return value + def set_cmd_end_reached(self, value): self.bits.cmd_end_reached = value + def get_cmd_end_reached(self): value = self.bits.cmd_end_reached; return value + def set_pmu_irq_raised(self, value): self.bits.pmu_irq_raised = value + def get_pmu_irq_raised(self): value = self.bits.pmu_irq_raised; return value + def set_wd_fault(self, value): self.bits.wd_fault = value + def get_wd_fault(self): value = self.bits.wd_fault; return value + def set_faulting_interface(self, value): self.bits.faulting_interface = value + def get_faulting_interface(self): value = self.bits.faulting_interface; return value + def set_faulting_channel(self, value): self.bits.faulting_channel = value + def get_faulting_channel(self): value = self.bits.faulting_channel; return value + def set_irq_history_mask(self, value): self.bits.irq_history_mask = value + def get_irq_history_mask(self): value = self.bits.irq_history_mask; return value -class ao_status_r(Union): +class cmd_r(Union): class _bitfield(Structure): _fields_ = [ - ("cmd_sbw_valid", c_uint32, 1), - ("cmd_act_valid", c_uint32, 1), - ("cmd_ctl_valid", c_uint32, 1), - ("cmd_scl_valid", c_uint32, 1), - ("cmd_sbr_valid", c_uint32, 1), - ("cmd_ofm_valid", c_uint32, 1), - ("blk_cmd_ready", c_uint32, 1), - ("blk_cmd_valid", c_uint32, 1), - ("reserved0", c_uint32, 8), - ("events", c_uint32, 8), - ("reserved1", c_uint32, 8), + ("transition_to_running_state", c_uint32, 1), + ("clear_irq", c_uint32, 1), + ("clock_q_enable", c_uint32, 1), + ("power_q_enable", c_uint32, 1), + ("stop_request", c_uint32, 1), + ("reserved0", c_uint32, 11), + ("clear_irq_history", c_uint32, 16), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_cmd_sbw_valid(self, value): self.bits.cmd_sbw_valid = value - def get_cmd_sbw_valid(self): value = self.bits.cmd_sbw_valid; return value - def set_cmd_act_valid(self, value): self.bits.cmd_act_valid = value - def get_cmd_act_valid(self): value = self.bits.cmd_act_valid; return value - def set_cmd_ctl_valid(self, value): self.bits.cmd_ctl_valid = value - def get_cmd_ctl_valid(self): value = self.bits.cmd_ctl_valid; return value - def set_cmd_scl_valid(self, value): self.bits.cmd_scl_valid = value - def get_cmd_scl_valid(self): value = self.bits.cmd_scl_valid; return value - def set_cmd_sbr_valid(self, value): self.bits.cmd_sbr_valid = value - def get_cmd_sbr_valid(self): value = self.bits.cmd_sbr_valid; return value - def set_cmd_ofm_valid(self, value): self.bits.cmd_ofm_valid = value - def get_cmd_ofm_valid(self): value = self.bits.cmd_ofm_valid; return value - def set_blk_cmd_ready(self, value): self.bits.blk_cmd_ready = value - def get_blk_cmd_ready(self): value = self.bits.blk_cmd_ready; return value - def set_blk_cmd_valid(self, value): self.bits.blk_cmd_valid = value - def get_blk_cmd_valid(self): value = self.bits.blk_cmd_valid; return value - def set_events(self, value): self.bits.events = value - def get_events(self): value = self.bits.events; return value + def set_transition_to_running_state(self, value): self.bits.transition_to_running_state = value + def get_transition_to_running_state(self): value = self.bits.transition_to_running_state; return value + def set_clear_irq(self, value): self.bits.clear_irq = value + def get_clear_irq(self): value = self.bits.clear_irq; return value + def set_clock_q_enable(self, value): self.bits.clock_q_enable = value + def get_clock_q_enable(self): value = self.bits.clock_q_enable; return value + def set_power_q_enable(self, value): self.bits.power_q_enable = value + def get_power_q_enable(self): value = self.bits.power_q_enable; return value + def set_stop_request(self, value): self.bits.stop_request = value + def get_stop_request(self): value = self.bits.stop_request; return value + def set_clear_irq_history(self, value): self.bits.clear_irq_history = value + def get_clear_irq_history(self): value = self.bits.clear_irq_history; return value -class dma_status0_r(Union): +class reset_r(Union): class _bitfield(Structure): _fields_ = [ - ("cmd_idle", c_uint32, 1), - ("ifm_idle", c_uint32, 1), - ("wgt_idle_c0", c_uint32, 1), - ("bas_idle_c0", c_uint32, 1), - ("m2m_idle", c_uint32, 1), - ("ofm_idle", c_uint32, 1), - ("halt_req", c_uint32, 1), - ("halt_ack", c_uint32, 1), - ("pause_req", c_uint32, 1), - ("pause_ack", c_uint32, 1), - ("ib0_ai_valid_c0", c_uint32, 1), - ("ib0_ai_ready_c0", c_uint32, 1), - ("ib1_ai_valid_c0", c_uint32, 1), - ("ib1_ai_ready_c0", c_uint32, 1), - ("ib0_ao_valid_c0", c_uint32, 1), - ("ib0_ao_ready_c0", c_uint32, 1), - ("ib1_ao_valid_c0", c_uint32, 1), - ("ib1_ao_ready_c0", c_uint32, 1), - ("ob0_valid_c0", c_uint32, 1), - ("ob0_ready_c0", c_uint32, 1), - ("ob1_valid_c0", c_uint32, 1), - ("ob1_ready_c0", c_uint32, 1), - ("cmd_valid", c_uint32, 1), - ("cmd_ready", c_uint32, 1), - ("wd_bitstream_valid_c0", c_uint32, 1), - ("wd_bitstream_ready_c0", c_uint32, 1), - ("bs_bitstream_valid_c0", c_uint32, 1), - ("bs_bitstream_ready_c0", c_uint32, 1), - ("axi0_ar_stalled", c_uint32, 1), - ("axi0_rd_limit_stall", c_uint32, 1), - ("axi0_aw_stalled", c_uint32, 1), - ("axi0_w_stalled", c_uint32, 1), + ("pending_cpl", c_uint32, 1), + ("pending_csl", c_uint32, 1), + ("reserved0", c_uint32, 30), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_cmd_idle(self, value): self.bits.cmd_idle = value - def get_cmd_idle(self): value = self.bits.cmd_idle; return value - def set_ifm_idle(self, value): self.bits.ifm_idle = value - def get_ifm_idle(self): value = self.bits.ifm_idle; return value - def set_wgt_idle_c0(self, value): self.bits.wgt_idle_c0 = value - def get_wgt_idle_c0(self): value = self.bits.wgt_idle_c0; return value - def set_bas_idle_c0(self, value): self.bits.bas_idle_c0 = value - def get_bas_idle_c0(self): value = self.bits.bas_idle_c0; return value - def set_m2m_idle(self, value): self.bits.m2m_idle = value - def get_m2m_idle(self): value = self.bits.m2m_idle; return value - def set_ofm_idle(self, value): self.bits.ofm_idle = value - def get_ofm_idle(self): value = self.bits.ofm_idle; return value - def set_halt_req(self, value): self.bits.halt_req = value - def get_halt_req(self): value = self.bits.halt_req; return value - def set_halt_ack(self, value): self.bits.halt_ack = value - def get_halt_ack(self): value = self.bits.halt_ack; return value - def set_pause_req(self, value): self.bits.pause_req = value - def get_pause_req(self): value = self.bits.pause_req; return value - def set_pause_ack(self, value): self.bits.pause_ack = value - def get_pause_ack(self): value = self.bits.pause_ack; return value - def set_ib0_ai_valid_c0(self, value): self.bits.ib0_ai_valid_c0 = value - def get_ib0_ai_valid_c0(self): value = self.bits.ib0_ai_valid_c0; return value - def set_ib0_ai_ready_c0(self, value): self.bits.ib0_ai_ready_c0 = value - def get_ib0_ai_ready_c0(self): value = self.bits.ib0_ai_ready_c0; return value - def set_ib1_ai_valid_c0(self, value): self.bits.ib1_ai_valid_c0 = value - def get_ib1_ai_valid_c0(self): value = self.bits.ib1_ai_valid_c0; return value - def set_ib1_ai_ready_c0(self, value): self.bits.ib1_ai_ready_c0 = value - def get_ib1_ai_ready_c0(self): value = self.bits.ib1_ai_ready_c0; return value - def set_ib0_ao_valid_c0(self, value): self.bits.ib0_ao_valid_c0 = value - def get_ib0_ao_valid_c0(self): value = self.bits.ib0_ao_valid_c0; return value - def set_ib0_ao_ready_c0(self, value): self.bits.ib0_ao_ready_c0 = value - def get_ib0_ao_ready_c0(self): value = self.bits.ib0_ao_ready_c0; return value - def set_ib1_ao_valid_c0(self, value): self.bits.ib1_ao_valid_c0 = value - def get_ib1_ao_valid_c0(self): value = self.bits.ib1_ao_valid_c0; return value - def set_ib1_ao_ready_c0(self, value): self.bits.ib1_ao_ready_c0 = value - def get_ib1_ao_ready_c0(self): value = self.bits.ib1_ao_ready_c0; return value - def set_ob0_valid_c0(self, value): self.bits.ob0_valid_c0 = value - def get_ob0_valid_c0(self): value = self.bits.ob0_valid_c0; return value - def set_ob0_ready_c0(self, value): self.bits.ob0_ready_c0 = value - def get_ob0_ready_c0(self): value = self.bits.ob0_ready_c0; return value - def set_ob1_valid_c0(self, value): self.bits.ob1_valid_c0 = value - def get_ob1_valid_c0(self): value = self.bits.ob1_valid_c0; return value - def set_ob1_ready_c0(self, value): self.bits.ob1_ready_c0 = value - def get_ob1_ready_c0(self): value = self.bits.ob1_ready_c0; return value - def set_cmd_valid(self, value): self.bits.cmd_valid = value - def get_cmd_valid(self): value = self.bits.cmd_valid; return value - def set_cmd_ready(self, value): self.bits.cmd_ready = value - def get_cmd_ready(self): value = self.bits.cmd_ready; return value - def set_wd_bitstream_valid_c0(self, value): self.bits.wd_bitstream_valid_c0 = value - def get_wd_bitstream_valid_c0(self): value = self.bits.wd_bitstream_valid_c0; return value - def set_wd_bitstream_ready_c0(self, value): self.bits.wd_bitstream_ready_c0 = value - def get_wd_bitstream_ready_c0(self): value = self.bits.wd_bitstream_ready_c0; return value - def set_bs_bitstream_valid_c0(self, value): self.bits.bs_bitstream_valid_c0 = value - def get_bs_bitstream_valid_c0(self): value = self.bits.bs_bitstream_valid_c0; return value - def set_bs_bitstream_ready_c0(self, value): self.bits.bs_bitstream_ready_c0 = value - def get_bs_bitstream_ready_c0(self): value = self.bits.bs_bitstream_ready_c0; return value - def set_axi0_ar_stalled(self, value): self.bits.axi0_ar_stalled = value - def get_axi0_ar_stalled(self): value = self.bits.axi0_ar_stalled; return value - def set_axi0_rd_limit_stall(self, value): self.bits.axi0_rd_limit_stall = value - def get_axi0_rd_limit_stall(self): value = self.bits.axi0_rd_limit_stall; return value - def set_axi0_aw_stalled(self, value): self.bits.axi0_aw_stalled = value - def get_axi0_aw_stalled(self): value = self.bits.axi0_aw_stalled; return value - def set_axi0_w_stalled(self, value): self.bits.axi0_w_stalled = value - def get_axi0_w_stalled(self): value = self.bits.axi0_w_stalled; return value + def set_pending_cpl(self, value): self.bits.pending_cpl = value + def get_pending_cpl(self): value = self.bits.pending_cpl; return value + def set_pending_csl(self, value): self.bits.pending_csl = value + def get_pending_csl(self): value = self.bits.pending_csl; return value -class dma_status1_r(Union): +class qbase0_r(Union): class _bitfield(Structure): _fields_ = [ - ("axi0_wr_limit_stall", c_uint32, 1), - ("axi1_ar_stalled", c_uint32, 1), - ("axi1_rd_limit_stall", c_uint32, 1), - ("axi1_wr_stalled", c_uint32, 1), - ("axi1_w_stalled", c_uint32, 1), - ("axi1_wr_limit_stall", c_uint32, 1), - ("wgt_idle_c1", c_uint32, 1), - ("bas_idle_c1", c_uint32, 1), - ("ib0_ai_valid_c1", c_uint32, 1), - ("ib0_ai_ready_c1", c_uint32, 1), - ("ib1_ai_valid_c1", c_uint32, 1), - ("ib1_ai_ready_c1", c_uint32, 1), - ("ib0_ao_valid_c1", c_uint32, 1), - ("ib0_ao_ready_c1", c_uint32, 1), - ("ib1_ao_valid_c1", c_uint32, 1), - ("ib1_ao_ready_c1", c_uint32, 1), - ("ob0_valid_c1", c_uint32, 1), - ("ob0_ready_c1", c_uint32, 1), - ("ob1_valid_c1", c_uint32, 1), - ("ob1_ready_c1", c_uint32, 1), - ("wd_bitstream_valid_c1", c_uint32, 1), - ("wd_bitstream_ready_c1", c_uint32, 1), - ("bs_bitstream_valid_c1", c_uint32, 1), - ("bs_bitstream_ready_c1", c_uint32, 1), - ("reserved0", c_uint32, 8), + ("qbase0", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_axi0_wr_limit_stall(self, value): self.bits.axi0_wr_limit_stall = value - def get_axi0_wr_limit_stall(self): value = self.bits.axi0_wr_limit_stall; return value - def set_axi1_ar_stalled(self, value): self.bits.axi1_ar_stalled = value - def get_axi1_ar_stalled(self): value = self.bits.axi1_ar_stalled; return value - def set_axi1_rd_limit_stall(self, value): self.bits.axi1_rd_limit_stall = value - def get_axi1_rd_limit_stall(self): value = self.bits.axi1_rd_limit_stall; return value - def set_axi1_wr_stalled(self, value): self.bits.axi1_wr_stalled = value - def get_axi1_wr_stalled(self): value = self.bits.axi1_wr_stalled; return value - def set_axi1_w_stalled(self, value): self.bits.axi1_w_stalled = value - def get_axi1_w_stalled(self): value = self.bits.axi1_w_stalled; return value - def set_axi1_wr_limit_stall(self, value): self.bits.axi1_wr_limit_stall = value - def get_axi1_wr_limit_stall(self): value = self.bits.axi1_wr_limit_stall; return value - def set_wgt_idle_c1(self, value): self.bits.wgt_idle_c1 = value - def get_wgt_idle_c1(self): value = self.bits.wgt_idle_c1; return value - def set_bas_idle_c1(self, value): self.bits.bas_idle_c1 = value - def get_bas_idle_c1(self): value = self.bits.bas_idle_c1; return value - def set_ib0_ai_valid_c1(self, value): self.bits.ib0_ai_valid_c1 = value - def get_ib0_ai_valid_c1(self): value = self.bits.ib0_ai_valid_c1; return value - def set_ib0_ai_ready_c1(self, value): self.bits.ib0_ai_ready_c1 = value - def get_ib0_ai_ready_c1(self): value = self.bits.ib0_ai_ready_c1; return value - def set_ib1_ai_valid_c1(self, value): self.bits.ib1_ai_valid_c1 = value - def get_ib1_ai_valid_c1(self): value = self.bits.ib1_ai_valid_c1; return value - def set_ib1_ai_ready_c1(self, value): self.bits.ib1_ai_ready_c1 = value - def get_ib1_ai_ready_c1(self): value = self.bits.ib1_ai_ready_c1; return value - def set_ib0_ao_valid_c1(self, value): self.bits.ib0_ao_valid_c1 = value - def get_ib0_ao_valid_c1(self): value = self.bits.ib0_ao_valid_c1; return value - def set_ib0_ao_ready_c1(self, value): self.bits.ib0_ao_ready_c1 = value - def get_ib0_ao_ready_c1(self): value = self.bits.ib0_ao_ready_c1; return value - def set_ib1_ao_valid_c1(self, value): self.bits.ib1_ao_valid_c1 = value - def get_ib1_ao_valid_c1(self): value = self.bits.ib1_ao_valid_c1; return value - def set_ib1_ao_ready_c1(self, value): self.bits.ib1_ao_ready_c1 = value - def get_ib1_ao_ready_c1(self): value = self.bits.ib1_ao_ready_c1; return value - def set_ob0_valid_c1(self, value): self.bits.ob0_valid_c1 = value - def get_ob0_valid_c1(self): value = self.bits.ob0_valid_c1; return value - def set_ob0_ready_c1(self, value): self.bits.ob0_ready_c1 = value - def get_ob0_ready_c1(self): value = self.bits.ob0_ready_c1; return value - def set_ob1_valid_c1(self, value): self.bits.ob1_valid_c1 = value - def get_ob1_valid_c1(self): value = self.bits.ob1_valid_c1; return value - def set_ob1_ready_c1(self, value): self.bits.ob1_ready_c1 = value - def get_ob1_ready_c1(self): value = self.bits.ob1_ready_c1; return value - def set_wd_bitstream_valid_c1(self, value): self.bits.wd_bitstream_valid_c1 = value - def get_wd_bitstream_valid_c1(self): value = self.bits.wd_bitstream_valid_c1; return value - def set_wd_bitstream_ready_c1(self, value): self.bits.wd_bitstream_ready_c1 = value - def get_wd_bitstream_ready_c1(self): value = self.bits.wd_bitstream_ready_c1; return value - def set_bs_bitstream_valid_c1(self, value): self.bits.bs_bitstream_valid_c1 = value - def get_bs_bitstream_valid_c1(self): value = self.bits.bs_bitstream_valid_c1; return value - def set_bs_bitstream_ready_c1(self, value): self.bits.bs_bitstream_ready_c1 = value - def get_bs_bitstream_ready_c1(self): value = self.bits.bs_bitstream_ready_c1; return value + def set_qbase0(self, value): self.bits.qbase0 = value + def get_qbase0(self): value = self.bits.qbase0; return value + + +class qbase1_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("qbase1", c_uint32, 32), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_qbase1(self, value): self.bits.qbase1 = value + def get_qbase1(self): value = self.bits.qbase1; return value + + +class qread_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("qread", c_uint32, 32), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_qread(self, value): self.bits.qread = value + def get_qread(self): value = self.bits.qread; return value + + +class qconfig_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("qconfig", c_uint32, 32), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_qconfig(self, value): self.bits.qconfig = value + def get_qconfig(self): value = self.bits.qconfig; return value + + +class qsize_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("qsize", c_uint32, 32), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_qsize(self, value): self.bits.qsize = value + def get_qsize(self): value = self.bits.qsize; return value + + +class prot_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("active_cpl", c_uint32, 1), + ("active_csl", c_uint32, 1), + ("reserved0", c_uint32, 30), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_active_cpl(self, value): self.bits.active_cpl = value + def get_active_cpl(self): value = self.bits.active_cpl; return value + def set_active_csl(self, value): self.bits.active_csl = value + def get_active_csl(self): value = self.bits.active_csl; return value + + +class config_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("macs_per_cc", c_uint32, 4), + ("cmd_stream_version", c_uint32, 4), + ("shram_size", c_uint32, 8), + ("reserved0", c_uint32, 12), + ("product", c_uint32, 4), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_macs_per_cc(self, value): self.bits.macs_per_cc = value + def get_macs_per_cc(self): value = self.bits.macs_per_cc; return value + def set_cmd_stream_version(self, value): self.bits.cmd_stream_version = value + def get_cmd_stream_version(self): value = self.bits.cmd_stream_version; return value + def set_shram_size(self, value): self.bits.shram_size = value + def get_shram_size(self): value = self.bits.shram_size; return value + def set_product(self, value): self.bits.product = value + def get_product(self): value = self.bits.product; return value + + +class lock_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("lock", c_uint32, 32), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_lock(self, value): self.bits.lock = value + def get_lock(self): value = self.bits.lock; return value + + +class regioncfg_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("region0", c_uint32, 2), + ("region1", c_uint32, 2), + ("region2", c_uint32, 2), + ("region3", c_uint32, 2), + ("region4", c_uint32, 2), + ("region5", c_uint32, 2), + ("region6", c_uint32, 2), + ("region7", c_uint32, 2), + ("reserved0", c_uint32, 16), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_region0(self, value): self.bits.region0 = value + def get_region0(self): value = self.bits.region0; return value + def set_region1(self, value): self.bits.region1 = value + def get_region1(self): value = self.bits.region1; return value + def set_region2(self, value): self.bits.region2 = value + def get_region2(self): value = self.bits.region2; return value + def set_region3(self, value): self.bits.region3 = value + def get_region3(self): value = self.bits.region3; return value + def set_region4(self, value): self.bits.region4 = value + def get_region4(self): value = self.bits.region4; return value + def set_region5(self, value): self.bits.region5 = value + def get_region5(self): value = self.bits.region5; return value + def set_region6(self, value): self.bits.region6 = value + def get_region6(self): value = self.bits.region6; return value + def set_region7(self, value): self.bits.region7 = value + def get_region7(self): value = self.bits.region7; return value + + +class axi_limit0_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("max_beats", c_uint32, 2), + ("reserved0", c_uint32, 2), + ("memtype", c_uint32, 4), + ("reserved1", c_uint32, 8), + ("max_outstanding_read_m1", c_uint32, 8), + ("max_outstanding_write_m1", c_uint32, 8), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_max_beats(self, value): self.bits.max_beats = value + def get_max_beats(self): value = self.bits.max_beats; return value + def set_memtype(self, value): self.bits.memtype = value + def get_memtype(self): value = self.bits.memtype; return value + def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value + def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value + def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value + def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value + + +class axi_limit1_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("max_beats", c_uint32, 2), + ("reserved0", c_uint32, 2), + ("memtype", c_uint32, 4), + ("reserved1", c_uint32, 8), + ("max_outstanding_read_m1", c_uint32, 8), + ("max_outstanding_write_m1", c_uint32, 8), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_max_beats(self, value): self.bits.max_beats = value + def get_max_beats(self): value = self.bits.max_beats; return value + def set_memtype(self, value): self.bits.memtype = value + def get_memtype(self): value = self.bits.memtype; return value + def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value + def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value + def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value + def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value -class clkforce_r(Union): +class axi_limit2_r(Union): class _bitfield(Structure): _fields_ = [ - ("top_level_clk", c_uint32, 1), - ("cc_clk", c_uint32, 1), - ("dma_clk", c_uint32, 1), - ("mac_clk", c_uint32, 1), - ("ao_clk", c_uint32, 1), - ("wd_clk", c_uint32, 1), - ("reserved0", c_uint32, 26), + ("max_beats", c_uint32, 2), + ("reserved0", c_uint32, 2), + ("memtype", c_uint32, 4), + ("reserved1", c_uint32, 8), + ("max_outstanding_read_m1", c_uint32, 8), + ("max_outstanding_write_m1", c_uint32, 8), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_top_level_clk(self, value): self.bits.top_level_clk = value - def get_top_level_clk(self): value = self.bits.top_level_clk; return value - def set_cc_clk(self, value): self.bits.cc_clk = value - def get_cc_clk(self): value = self.bits.cc_clk; return value - def set_dma_clk(self, value): self.bits.dma_clk = value - def get_dma_clk(self): value = self.bits.dma_clk; return value - def set_mac_clk(self, value): self.bits.mac_clk = value - def get_mac_clk(self): value = self.bits.mac_clk; return value - def set_ao_clk(self, value): self.bits.ao_clk = value - def get_ao_clk(self): value = self.bits.ao_clk; return value - def set_wd_clk(self, value): self.bits.wd_clk = value - def get_wd_clk(self): value = self.bits.wd_clk; return value + def set_max_beats(self, value): self.bits.max_beats = value + def get_max_beats(self): value = self.bits.max_beats; return value + def set_memtype(self, value): self.bits.memtype = value + def get_memtype(self): value = self.bits.memtype; return value + def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value + def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value + def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value + def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value + + +class axi_limit3_r(Union): + class _bitfield(Structure): + _fields_ = [ + ("max_beats", c_uint32, 2), + ("reserved0", c_uint32, 2), + ("memtype", c_uint32, 4), + ("reserved1", c_uint32, 8), + ("max_outstanding_read_m1", c_uint32, 8), + ("max_outstanding_write_m1", c_uint32, 8), + ] + _fields_ = [("bits", _bitfield), + ("word", c_uint32)] + def set_max_beats(self, value): self.bits.max_beats = value + def get_max_beats(self): value = self.bits.max_beats; return value + def set_memtype(self, value): self.bits.memtype = value + def get_memtype(self): value = self.bits.memtype; return value + def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value + def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value + def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value + def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value class basep0_r(Union): @@ -1333,472 +1320,485 @@ class basep15_r(Union): def get_addr_word(self): value = self.bits.addr_word; return value -class pid4_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid4", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid4(self, value): self.bits.pid4 = value - def get_pid4(self): value = self.bits.pid4; return value - - -class pid5_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid5", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid5(self, value): self.bits.pid5 = value - def get_pid5(self): value = self.bits.pid5; return value - - -class pid6_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid6", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid6(self, value): self.bits.pid6 = value - def get_pid6(self): value = self.bits.pid6; return value - - -class pid7_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid7", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid7(self, value): self.bits.pid7 = value - def get_pid7(self): value = self.bits.pid7; return value - - -class pid0_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid0", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid0(self, value): self.bits.pid0 = value - def get_pid0(self): value = self.bits.pid0; return value - - -class pid1_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid1", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid1(self, value): self.bits.pid1 = value - def get_pid1(self): value = self.bits.pid1; return value - - -class pid2_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid2", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid2(self, value): self.bits.pid2 = value - def get_pid2(self): value = self.bits.pid2; return value - - -class pid3_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("pid3", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_pid3(self, value): self.bits.pid3 = value - def get_pid3(self): value = self.bits.pid3; return value - - -class cid0_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("cid0", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_cid0(self, value): self.bits.cid0 = value - def get_cid0(self): value = self.bits.cid0; return value - - -class cid1_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("cid1", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_cid1(self, value): self.bits.cid1 = value - def get_cid1(self): value = self.bits.cid1; return value - - -class cid2_r(Union): - class _bitfield(Structure): - _fields_ = [ - ("cid2", c_uint32, 32), - ] - _fields_ = [("bits", _bitfield), - ("word", c_uint32)] - def set_cid2(self, value): self.bits.cid2 = value - def get_cid2(self): value = self.bits.cid2; return value - - -class cid3_r(Union): +class wd_status_r(Union): class _bitfield(Structure): _fields_ = [ - ("cid3", c_uint32, 32), + ("core_slice_state", c_uint32, 2), + ("core_idle", c_uint32, 1), + ("ctrl_state", c_uint32, 2), + ("ctrl_idle", c_uint32, 1), + ("write_buf_index0", c_uint32, 3), + ("write_buf_valid0", c_uint32, 1), + ("write_buf_idle0", c_uint32, 1), + ("write_buf_index1", c_uint32, 3), + ("write_buf_valid1", c_uint32, 1), + ("write_buf_idle1", c_uint32, 1), + ("events", c_uint32, 12), + ("reserved0", c_uint32, 4), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_cid3(self, value): self.bits.cid3 = value - def get_cid3(self): value = self.bits.cid3; return value + def set_core_slice_state(self, value): self.bits.core_slice_state = value + def get_core_slice_state(self): value = self.bits.core_slice_state; return value + def set_core_idle(self, value): self.bits.core_idle = value + def get_core_idle(self): value = self.bits.core_idle; return value + def set_ctrl_state(self, value): self.bits.ctrl_state = value + def get_ctrl_state(self): value = self.bits.ctrl_state; return value + def set_ctrl_idle(self, value): self.bits.ctrl_idle = value + def get_ctrl_idle(self): value = self.bits.ctrl_idle; return value + def set_write_buf_index0(self, value): self.bits.write_buf_index0 = value + def get_write_buf_index0(self): value = self.bits.write_buf_index0; return value + def set_write_buf_valid0(self, value): self.bits.write_buf_valid0 = value + def get_write_buf_valid0(self): value = self.bits.write_buf_valid0; return value + def set_write_buf_idle0(self, value): self.bits.write_buf_idle0 = value + def get_write_buf_idle0(self): value = self.bits.write_buf_idle0; return value + def set_write_buf_index1(self, value): self.bits.write_buf_index1 = value + def get_write_buf_index1(self): value = self.bits.write_buf_index1; return value + def set_write_buf_valid1(self, value): self.bits.write_buf_valid1 = value + def get_write_buf_valid1(self): value = self.bits.write_buf_valid1; return value + def set_write_buf_idle1(self, value): self.bits.write_buf_idle1 = value + def get_write_buf_idle1(self): value = self.bits.write_buf_idle1; return value + def set_events(self, value): self.bits.events = value + def get_events(self): value = self.bits.events; return value -class id_r(Union): +class mac_status_r(Union): class _bitfield(Structure): _fields_ = [ - ("version_status", c_uint32, 4), - ("version_minor", c_uint32, 4), - ("version_major", c_uint32, 4), - ("product_major", c_uint32, 4), - ("arch_patch_rev", c_uint32, 4), - ("arch_minor_rev", c_uint32, 8), - ("arch_major_rev", c_uint32, 4), + ("block_cfg_valid", c_uint32, 1), + ("trav_en", c_uint32, 1), + ("wait_for_ib", c_uint32, 1), + ("wait_for_acc_buf", c_uint32, 1), + ("wait_for_weights", c_uint32, 1), + ("stall_stripe", c_uint32, 1), + ("dw_sel", c_uint32, 1), + ("wait_for_dw0_ready", c_uint32, 1), + ("wait_for_dw1_ready", c_uint32, 1), + ("acc_buf_sel_ai", c_uint32, 1), + ("wait_for_acc0_ready", c_uint32, 1), + ("wait_for_acc1_ready", c_uint32, 1), + ("acc_buf_sel_aa", c_uint32, 1), + ("acc0_valid", c_uint32, 1), + ("acc1_valid", c_uint32, 1), + ("reserved0", c_uint32, 1), + ("events", c_uint32, 11), + ("reserved1", c_uint32, 5), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_version_status(self, value): self.bits.version_status = value - def get_version_status(self): value = self.bits.version_status; return value - def set_version_minor(self, value): self.bits.version_minor = value - def get_version_minor(self): value = self.bits.version_minor; return value - def set_version_major(self, value): self.bits.version_major = value - def get_version_major(self): value = self.bits.version_major; return value - def set_product_major(self, value): self.bits.product_major = value - def get_product_major(self): value = self.bits.product_major; return value - def set_arch_patch_rev(self, value): self.bits.arch_patch_rev = value - def get_arch_patch_rev(self): value = self.bits.arch_patch_rev; return value - def set_arch_minor_rev(self, value): self.bits.arch_minor_rev = value - def get_arch_minor_rev(self): value = self.bits.arch_minor_rev; return value - def set_arch_major_rev(self, value): self.bits.arch_major_rev = value - def get_arch_major_rev(self): value = self.bits.arch_major_rev; return value + def set_block_cfg_valid(self, value): self.bits.block_cfg_valid = value + def get_block_cfg_valid(self): value = self.bits.block_cfg_valid; return value + def set_trav_en(self, value): self.bits.trav_en = value + def get_trav_en(self): value = self.bits.trav_en; return value + def set_wait_for_ib(self, value): self.bits.wait_for_ib = value + def get_wait_for_ib(self): value = self.bits.wait_for_ib; return value + def set_wait_for_acc_buf(self, value): self.bits.wait_for_acc_buf = value + def get_wait_for_acc_buf(self): value = self.bits.wait_for_acc_buf; return value + def set_wait_for_weights(self, value): self.bits.wait_for_weights = value + def get_wait_for_weights(self): value = self.bits.wait_for_weights; return value + def set_stall_stripe(self, value): self.bits.stall_stripe = value + def get_stall_stripe(self): value = self.bits.stall_stripe; return value + def set_dw_sel(self, value): self.bits.dw_sel = value + def get_dw_sel(self): value = self.bits.dw_sel; return value + def set_wait_for_dw0_ready(self, value): self.bits.wait_for_dw0_ready = value + def get_wait_for_dw0_ready(self): value = self.bits.wait_for_dw0_ready; return value + def set_wait_for_dw1_ready(self, value): self.bits.wait_for_dw1_ready = value + def get_wait_for_dw1_ready(self): value = self.bits.wait_for_dw1_ready; return value + def set_acc_buf_sel_ai(self, value): self.bits.acc_buf_sel_ai = value + def get_acc_buf_sel_ai(self): value = self.bits.acc_buf_sel_ai; return value + def set_wait_for_acc0_ready(self, value): self.bits.wait_for_acc0_ready = value + def get_wait_for_acc0_ready(self): value = self.bits.wait_for_acc0_ready; return value + def set_wait_for_acc1_ready(self, value): self.bits.wait_for_acc1_ready = value + def get_wait_for_acc1_ready(self): value = self.bits.wait_for_acc1_ready; return value + def set_acc_buf_sel_aa(self, value): self.bits.acc_buf_sel_aa = value + def get_acc_buf_sel_aa(self): value = self.bits.acc_buf_sel_aa; return value + def set_acc0_valid(self, value): self.bits.acc0_valid = value + def get_acc0_valid(self): value = self.bits.acc0_valid; return value + def set_acc1_valid(self, value): self.bits.acc1_valid = value + def get_acc1_valid(self): value = self.bits.acc1_valid; return value + def set_events(self, value): self.bits.events = value + def get_events(self): value = self.bits.events; return value -class status_r(Union): +class ao_status_r(Union): class _bitfield(Structure): _fields_ = [ - ("state", c_uint32, 1), - ("irq_raised", c_uint32, 1), - ("bus_status", c_uint32, 1), - ("reset_status", c_uint32, 1), - ("cmd_parse_error", c_uint32, 1), - ("cmd_end_reached", c_uint32, 1), - ("pmu_irq_raised", c_uint32, 1), - ("wd_fault", c_uint32, 1), - ("reserved0", c_uint32, 3), - ("faulting_interface", c_uint32, 1), - ("faulting_channel", c_uint32, 4), - ("irq_history_mask", c_uint32, 16), + ("cmd_sbw_valid", c_uint32, 1), + ("cmd_act_valid", c_uint32, 1), + ("cmd_ctl_valid", c_uint32, 1), + ("cmd_scl_valid", c_uint32, 1), + ("cmd_sbr_valid", c_uint32, 1), + ("cmd_ofm_valid", c_uint32, 1), + ("blk_cmd_ready", c_uint32, 1), + ("blk_cmd_valid", c_uint32, 1), + ("reserved0", c_uint32, 8), + ("events", c_uint32, 8), + ("reserved1", c_uint32, 8), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_state(self, value): self.bits.state = value - def get_state(self): value = self.bits.state; return value - def set_irq_raised(self, value): self.bits.irq_raised = value - def get_irq_raised(self): value = self.bits.irq_raised; return value - def set_bus_status(self, value): self.bits.bus_status = value - def get_bus_status(self): value = self.bits.bus_status; return value - def set_reset_status(self, value): self.bits.reset_status = value - def get_reset_status(self): value = self.bits.reset_status; return value - def set_cmd_parse_error(self, value): self.bits.cmd_parse_error = value - def get_cmd_parse_error(self): value = self.bits.cmd_parse_error; return value - def set_cmd_end_reached(self, value): self.bits.cmd_end_reached = value - def get_cmd_end_reached(self): value = self.bits.cmd_end_reached; return value - def set_pmu_irq_raised(self, value): self.bits.pmu_irq_raised = value - def get_pmu_irq_raised(self): value = self.bits.pmu_irq_raised; return value - def set_wd_fault(self, value): self.bits.wd_fault = value - def get_wd_fault(self): value = self.bits.wd_fault; return value - def set_faulting_interface(self, value): self.bits.faulting_interface = value - def get_faulting_interface(self): value = self.bits.faulting_interface; return value - def set_faulting_channel(self, value): self.bits.faulting_channel = value - def get_faulting_channel(self): value = self.bits.faulting_channel; return value - def set_irq_history_mask(self, value): self.bits.irq_history_mask = value - def get_irq_history_mask(self): value = self.bits.irq_history_mask; return value + def set_cmd_sbw_valid(self, value): self.bits.cmd_sbw_valid = value + def get_cmd_sbw_valid(self): value = self.bits.cmd_sbw_valid; return value + def set_cmd_act_valid(self, value): self.bits.cmd_act_valid = value + def get_cmd_act_valid(self): value = self.bits.cmd_act_valid; return value + def set_cmd_ctl_valid(self, value): self.bits.cmd_ctl_valid = value + def get_cmd_ctl_valid(self): value = self.bits.cmd_ctl_valid; return value + def set_cmd_scl_valid(self, value): self.bits.cmd_scl_valid = value + def get_cmd_scl_valid(self): value = self.bits.cmd_scl_valid; return value + def set_cmd_sbr_valid(self, value): self.bits.cmd_sbr_valid = value + def get_cmd_sbr_valid(self): value = self.bits.cmd_sbr_valid; return value + def set_cmd_ofm_valid(self, value): self.bits.cmd_ofm_valid = value + def get_cmd_ofm_valid(self): value = self.bits.cmd_ofm_valid; return value + def set_blk_cmd_ready(self, value): self.bits.blk_cmd_ready = value + def get_blk_cmd_ready(self): value = self.bits.blk_cmd_ready; return value + def set_blk_cmd_valid(self, value): self.bits.blk_cmd_valid = value + def get_blk_cmd_valid(self): value = self.bits.blk_cmd_valid; return value + def set_events(self, value): self.bits.events = value + def get_events(self): value = self.bits.events; return value -class cmd_r(Union): +class dma_status0_r(Union): class _bitfield(Structure): _fields_ = [ - ("transition_to_running_state", c_uint32, 1), - ("clear_irq", c_uint32, 1), - ("clock_q_enable", c_uint32, 1), - ("power_q_enable", c_uint32, 1), - ("stop_request", c_uint32, 1), - ("reserved0", c_uint32, 11), - ("clear_irq_history", c_uint32, 16), + ("cmd_idle", c_uint32, 1), + ("ifm_idle", c_uint32, 1), + ("wgt_idle_c0", c_uint32, 1), + ("bas_idle_c0", c_uint32, 1), + ("m2m_idle", c_uint32, 1), + ("ofm_idle", c_uint32, 1), + ("halt_req", c_uint32, 1), + ("halt_ack", c_uint32, 1), + ("pause_req", c_uint32, 1), + ("pause_ack", c_uint32, 1), + ("ib0_ai_valid_c0", c_uint32, 1), + ("ib0_ai_ready_c0", c_uint32, 1), + ("ib1_ai_valid_c0", c_uint32, 1), + ("ib1_ai_ready_c0", c_uint32, 1), + ("ib0_ao_valid_c0", c_uint32, 1), + ("ib0_ao_ready_c0", c_uint32, 1), + ("ib1_ao_valid_c0", c_uint32, 1), + ("ib1_ao_ready_c0", c_uint32, 1), + ("ob0_valid_c0", c_uint32, 1), + ("ob0_ready_c0", c_uint32, 1), + ("ob1_valid_c0", c_uint32, 1), + ("ob1_ready_c0", c_uint32, 1), + ("cmd_valid", c_uint32, 1), + ("cmd_ready", c_uint32, 1), + ("wd_bitstream_valid_c0", c_uint32, 1), + ("wd_bitstream_ready_c0", c_uint32, 1), + ("bs_bitstream_valid_c0", c_uint32, 1), + ("bs_bitstream_ready_c0", c_uint32, 1), + ("axi0_ar_stalled", c_uint32, 1), + ("axi0_rd_limit_stall", c_uint32, 1), + ("axi0_aw_stalled", c_uint32, 1), + ("axi0_w_stalled", c_uint32, 1), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_transition_to_running_state(self, value): self.bits.transition_to_running_state = value - def get_transition_to_running_state(self): value = self.bits.transition_to_running_state; return value - def set_clear_irq(self, value): self.bits.clear_irq = value - def get_clear_irq(self): value = self.bits.clear_irq; return value - def set_clock_q_enable(self, value): self.bits.clock_q_enable = value - def get_clock_q_enable(self): value = self.bits.clock_q_enable; return value - def set_power_q_enable(self, value): self.bits.power_q_enable = value - def get_power_q_enable(self): value = self.bits.power_q_enable; return value - def set_stop_request(self, value): self.bits.stop_request = value - def get_stop_request(self): value = self.bits.stop_request; return value - def set_clear_irq_history(self, value): self.bits.clear_irq_history = value - def get_clear_irq_history(self): value = self.bits.clear_irq_history; return value + def set_cmd_idle(self, value): self.bits.cmd_idle = value + def get_cmd_idle(self): value = self.bits.cmd_idle; return value + def set_ifm_idle(self, value): self.bits.ifm_idle = value + def get_ifm_idle(self): value = self.bits.ifm_idle; return value + def set_wgt_idle_c0(self, value): self.bits.wgt_idle_c0 = value + def get_wgt_idle_c0(self): value = self.bits.wgt_idle_c0; return value + def set_bas_idle_c0(self, value): self.bits.bas_idle_c0 = value + def get_bas_idle_c0(self): value = self.bits.bas_idle_c0; return value + def set_m2m_idle(self, value): self.bits.m2m_idle = value + def get_m2m_idle(self): value = self.bits.m2m_idle; return value + def set_ofm_idle(self, value): self.bits.ofm_idle = value + def get_ofm_idle(self): value = self.bits.ofm_idle; return value + def set_halt_req(self, value): self.bits.halt_req = value + def get_halt_req(self): value = self.bits.halt_req; return value + def set_halt_ack(self, value): self.bits.halt_ack = value + def get_halt_ack(self): value = self.bits.halt_ack; return value + def set_pause_req(self, value): self.bits.pause_req = value + def get_pause_req(self): value = self.bits.pause_req; return value + def set_pause_ack(self, value): self.bits.pause_ack = value + def get_pause_ack(self): value = self.bits.pause_ack; return value + def set_ib0_ai_valid_c0(self, value): self.bits.ib0_ai_valid_c0 = value + def get_ib0_ai_valid_c0(self): value = self.bits.ib0_ai_valid_c0; return value + def set_ib0_ai_ready_c0(self, value): self.bits.ib0_ai_ready_c0 = value + def get_ib0_ai_ready_c0(self): value = self.bits.ib0_ai_ready_c0; return value + def set_ib1_ai_valid_c0(self, value): self.bits.ib1_ai_valid_c0 = value + def get_ib1_ai_valid_c0(self): value = self.bits.ib1_ai_valid_c0; return value + def set_ib1_ai_ready_c0(self, value): self.bits.ib1_ai_ready_c0 = value + def get_ib1_ai_ready_c0(self): value = self.bits.ib1_ai_ready_c0; return value + def set_ib0_ao_valid_c0(self, value): self.bits.ib0_ao_valid_c0 = value + def get_ib0_ao_valid_c0(self): value = self.bits.ib0_ao_valid_c0; return value + def set_ib0_ao_ready_c0(self, value): self.bits.ib0_ao_ready_c0 = value + def get_ib0_ao_ready_c0(self): value = self.bits.ib0_ao_ready_c0; return value + def set_ib1_ao_valid_c0(self, value): self.bits.ib1_ao_valid_c0 = value + def get_ib1_ao_valid_c0(self): value = self.bits.ib1_ao_valid_c0; return value + def set_ib1_ao_ready_c0(self, value): self.bits.ib1_ao_ready_c0 = value + def get_ib1_ao_ready_c0(self): value = self.bits.ib1_ao_ready_c0; return value + def set_ob0_valid_c0(self, value): self.bits.ob0_valid_c0 = value + def get_ob0_valid_c0(self): value = self.bits.ob0_valid_c0; return value + def set_ob0_ready_c0(self, value): self.bits.ob0_ready_c0 = value + def get_ob0_ready_c0(self): value = self.bits.ob0_ready_c0; return value + def set_ob1_valid_c0(self, value): self.bits.ob1_valid_c0 = value + def get_ob1_valid_c0(self): value = self.bits.ob1_valid_c0; return value + def set_ob1_ready_c0(self, value): self.bits.ob1_ready_c0 = value + def get_ob1_ready_c0(self): value = self.bits.ob1_ready_c0; return value + def set_cmd_valid(self, value): self.bits.cmd_valid = value + def get_cmd_valid(self): value = self.bits.cmd_valid; return value + def set_cmd_ready(self, value): self.bits.cmd_ready = value + def get_cmd_ready(self): value = self.bits.cmd_ready; return value + def set_wd_bitstream_valid_c0(self, value): self.bits.wd_bitstream_valid_c0 = value + def get_wd_bitstream_valid_c0(self): value = self.bits.wd_bitstream_valid_c0; return value + def set_wd_bitstream_ready_c0(self, value): self.bits.wd_bitstream_ready_c0 = value + def get_wd_bitstream_ready_c0(self): value = self.bits.wd_bitstream_ready_c0; return value + def set_bs_bitstream_valid_c0(self, value): self.bits.bs_bitstream_valid_c0 = value + def get_bs_bitstream_valid_c0(self): value = self.bits.bs_bitstream_valid_c0; return value + def set_bs_bitstream_ready_c0(self, value): self.bits.bs_bitstream_ready_c0 = value + def get_bs_bitstream_ready_c0(self): value = self.bits.bs_bitstream_ready_c0; return value + def set_axi0_ar_stalled(self, value): self.bits.axi0_ar_stalled = value + def get_axi0_ar_stalled(self): value = self.bits.axi0_ar_stalled; return value + def set_axi0_rd_limit_stall(self, value): self.bits.axi0_rd_limit_stall = value + def get_axi0_rd_limit_stall(self): value = self.bits.axi0_rd_limit_stall; return value + def set_axi0_aw_stalled(self, value): self.bits.axi0_aw_stalled = value + def get_axi0_aw_stalled(self): value = self.bits.axi0_aw_stalled; return value + def set_axi0_w_stalled(self, value): self.bits.axi0_w_stalled = value + def get_axi0_w_stalled(self): value = self.bits.axi0_w_stalled; return value -class reset_r(Union): +class dma_status1_r(Union): class _bitfield(Structure): _fields_ = [ - ("pending_cpl", c_uint32, 1), - ("pending_csl", c_uint32, 1), - ("reserved0", c_uint32, 30), + ("axi0_wr_limit_stall", c_uint32, 1), + ("axi1_ar_stalled", c_uint32, 1), + ("axi1_rd_limit_stall", c_uint32, 1), + ("axi1_wr_stalled", c_uint32, 1), + ("axi1_w_stalled", c_uint32, 1), + ("axi1_wr_limit_stall", c_uint32, 1), + ("wgt_idle_c1", c_uint32, 1), + ("bas_idle_c1", c_uint32, 1), + ("ib0_ai_valid_c1", c_uint32, 1), + ("ib0_ai_ready_c1", c_uint32, 1), + ("ib1_ai_valid_c1", c_uint32, 1), + ("ib1_ai_ready_c1", c_uint32, 1), + ("ib0_ao_valid_c1", c_uint32, 1), + ("ib0_ao_ready_c1", c_uint32, 1), + ("ib1_ao_valid_c1", c_uint32, 1), + ("ib1_ao_ready_c1", c_uint32, 1), + ("ob0_valid_c1", c_uint32, 1), + ("ob0_ready_c1", c_uint32, 1), + ("ob1_valid_c1", c_uint32, 1), + ("ob1_ready_c1", c_uint32, 1), + ("wd_bitstream_valid_c1", c_uint32, 1), + ("wd_bitstream_ready_c1", c_uint32, 1), + ("bs_bitstream_valid_c1", c_uint32, 1), + ("bs_bitstream_ready_c1", c_uint32, 1), + ("reserved0", c_uint32, 8), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_pending_cpl(self, value): self.bits.pending_cpl = value - def get_pending_cpl(self): value = self.bits.pending_cpl; return value - def set_pending_csl(self, value): self.bits.pending_csl = value - def get_pending_csl(self): value = self.bits.pending_csl; return value + def set_axi0_wr_limit_stall(self, value): self.bits.axi0_wr_limit_stall = value + def get_axi0_wr_limit_stall(self): value = self.bits.axi0_wr_limit_stall; return value + def set_axi1_ar_stalled(self, value): self.bits.axi1_ar_stalled = value + def get_axi1_ar_stalled(self): value = self.bits.axi1_ar_stalled; return value + def set_axi1_rd_limit_stall(self, value): self.bits.axi1_rd_limit_stall = value + def get_axi1_rd_limit_stall(self): value = self.bits.axi1_rd_limit_stall; return value + def set_axi1_wr_stalled(self, value): self.bits.axi1_wr_stalled = value + def get_axi1_wr_stalled(self): value = self.bits.axi1_wr_stalled; return value + def set_axi1_w_stalled(self, value): self.bits.axi1_w_stalled = value + def get_axi1_w_stalled(self): value = self.bits.axi1_w_stalled; return value + def set_axi1_wr_limit_stall(self, value): self.bits.axi1_wr_limit_stall = value + def get_axi1_wr_limit_stall(self): value = self.bits.axi1_wr_limit_stall; return value + def set_wgt_idle_c1(self, value): self.bits.wgt_idle_c1 = value + def get_wgt_idle_c1(self): value = self.bits.wgt_idle_c1; return value + def set_bas_idle_c1(self, value): self.bits.bas_idle_c1 = value + def get_bas_idle_c1(self): value = self.bits.bas_idle_c1; return value + def set_ib0_ai_valid_c1(self, value): self.bits.ib0_ai_valid_c1 = value + def get_ib0_ai_valid_c1(self): value = self.bits.ib0_ai_valid_c1; return value + def set_ib0_ai_ready_c1(self, value): self.bits.ib0_ai_ready_c1 = value + def get_ib0_ai_ready_c1(self): value = self.bits.ib0_ai_ready_c1; return value + def set_ib1_ai_valid_c1(self, value): self.bits.ib1_ai_valid_c1 = value + def get_ib1_ai_valid_c1(self): value = self.bits.ib1_ai_valid_c1; return value + def set_ib1_ai_ready_c1(self, value): self.bits.ib1_ai_ready_c1 = value + def get_ib1_ai_ready_c1(self): value = self.bits.ib1_ai_ready_c1; return value + def set_ib0_ao_valid_c1(self, value): self.bits.ib0_ao_valid_c1 = value + def get_ib0_ao_valid_c1(self): value = self.bits.ib0_ao_valid_c1; return value + def set_ib0_ao_ready_c1(self, value): self.bits.ib0_ao_ready_c1 = value + def get_ib0_ao_ready_c1(self): value = self.bits.ib0_ao_ready_c1; return value + def set_ib1_ao_valid_c1(self, value): self.bits.ib1_ao_valid_c1 = value + def get_ib1_ao_valid_c1(self): value = self.bits.ib1_ao_valid_c1; return value + def set_ib1_ao_ready_c1(self, value): self.bits.ib1_ao_ready_c1 = value + def get_ib1_ao_ready_c1(self): value = self.bits.ib1_ao_ready_c1; return value + def set_ob0_valid_c1(self, value): self.bits.ob0_valid_c1 = value + def get_ob0_valid_c1(self): value = self.bits.ob0_valid_c1; return value + def set_ob0_ready_c1(self, value): self.bits.ob0_ready_c1 = value + def get_ob0_ready_c1(self): value = self.bits.ob0_ready_c1; return value + def set_ob1_valid_c1(self, value): self.bits.ob1_valid_c1 = value + def get_ob1_valid_c1(self): value = self.bits.ob1_valid_c1; return value + def set_ob1_ready_c1(self, value): self.bits.ob1_ready_c1 = value + def get_ob1_ready_c1(self): value = self.bits.ob1_ready_c1; return value + def set_wd_bitstream_valid_c1(self, value): self.bits.wd_bitstream_valid_c1 = value + def get_wd_bitstream_valid_c1(self): value = self.bits.wd_bitstream_valid_c1; return value + def set_wd_bitstream_ready_c1(self, value): self.bits.wd_bitstream_ready_c1 = value + def get_wd_bitstream_ready_c1(self): value = self.bits.wd_bitstream_ready_c1; return value + def set_bs_bitstream_valid_c1(self, value): self.bits.bs_bitstream_valid_c1 = value + def get_bs_bitstream_valid_c1(self): value = self.bits.bs_bitstream_valid_c1; return value + def set_bs_bitstream_ready_c1(self, value): self.bits.bs_bitstream_ready_c1 = value + def get_bs_bitstream_ready_c1(self): value = self.bits.bs_bitstream_ready_c1; return value -class qbase0_r(Union): +class clkforce_r(Union): class _bitfield(Structure): _fields_ = [ - ("qbase0", c_uint32, 32), + ("top_level_clk", c_uint32, 1), + ("cc_clk", c_uint32, 1), + ("dma_clk", c_uint32, 1), + ("mac_clk", c_uint32, 1), + ("ao_clk", c_uint32, 1), + ("wd_clk", c_uint32, 1), + ("reserved0", c_uint32, 26), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_qbase0(self, value): self.bits.qbase0 = value - def get_qbase0(self): value = self.bits.qbase0; return value + def set_top_level_clk(self, value): self.bits.top_level_clk = value + def get_top_level_clk(self): value = self.bits.top_level_clk; return value + def set_cc_clk(self, value): self.bits.cc_clk = value + def get_cc_clk(self): value = self.bits.cc_clk; return value + def set_dma_clk(self, value): self.bits.dma_clk = value + def get_dma_clk(self): value = self.bits.dma_clk; return value + def set_mac_clk(self, value): self.bits.mac_clk = value + def get_mac_clk(self): value = self.bits.mac_clk; return value + def set_ao_clk(self, value): self.bits.ao_clk = value + def get_ao_clk(self): value = self.bits.ao_clk; return value + def set_wd_clk(self, value): self.bits.wd_clk = value + def get_wd_clk(self): value = self.bits.wd_clk; return value -class qbase1_r(Union): +class pid4_r(Union): class _bitfield(Structure): _fields_ = [ - ("qbase1", c_uint32, 32), + ("pid4", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_qbase1(self, value): self.bits.qbase1 = value - def get_qbase1(self): value = self.bits.qbase1; return value + def set_pid4(self, value): self.bits.pid4 = value + def get_pid4(self): value = self.bits.pid4; return value -class qread_r(Union): +class pid5_r(Union): class _bitfield(Structure): _fields_ = [ - ("qread", c_uint32, 32), + ("pid5", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_qread(self, value): self.bits.qread = value - def get_qread(self): value = self.bits.qread; return value + def set_pid5(self, value): self.bits.pid5 = value + def get_pid5(self): value = self.bits.pid5; return value -class qconfig_r(Union): +class pid6_r(Union): class _bitfield(Structure): _fields_ = [ - ("qconfig", c_uint32, 32), + ("pid6", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_qconfig(self, value): self.bits.qconfig = value - def get_qconfig(self): value = self.bits.qconfig; return value + def set_pid6(self, value): self.bits.pid6 = value + def get_pid6(self): value = self.bits.pid6; return value -class qsize_r(Union): +class pid7_r(Union): class _bitfield(Structure): _fields_ = [ - ("qsize", c_uint32, 32), + ("pid7", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_qsize(self, value): self.bits.qsize = value - def get_qsize(self): value = self.bits.qsize; return value + def set_pid7(self, value): self.bits.pid7 = value + def get_pid7(self): value = self.bits.pid7; return value -class prot_r(Union): +class pid0_r(Union): class _bitfield(Structure): _fields_ = [ - ("active_cpl", c_uint32, 1), - ("active_csl", c_uint32, 1), - ("reserved0", c_uint32, 30), + ("pid0", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_active_cpl(self, value): self.bits.active_cpl = value - def get_active_cpl(self): value = self.bits.active_cpl; return value - def set_active_csl(self, value): self.bits.active_csl = value - def get_active_csl(self): value = self.bits.active_csl; return value + def set_pid0(self, value): self.bits.pid0 = value + def get_pid0(self): value = self.bits.pid0; return value -class config_r(Union): +class pid1_r(Union): class _bitfield(Structure): _fields_ = [ - ("macs_per_cc", c_uint32, 4), - ("cmd_stream_version", c_uint32, 4), - ("shram_size", c_uint32, 8), - ("reserved0", c_uint32, 12), - ("product", c_uint32, 4), + ("pid1", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_macs_per_cc(self, value): self.bits.macs_per_cc = value - def get_macs_per_cc(self): value = self.bits.macs_per_cc; return value - def set_cmd_stream_version(self, value): self.bits.cmd_stream_version = value - def get_cmd_stream_version(self): value = self.bits.cmd_stream_version; return value - def set_shram_size(self, value): self.bits.shram_size = value - def get_shram_size(self): value = self.bits.shram_size; return value - def set_product(self, value): self.bits.product = value - def get_product(self): value = self.bits.product; return value + def set_pid1(self, value): self.bits.pid1 = value + def get_pid1(self): value = self.bits.pid1; return value -class lock_r(Union): +class pid2_r(Union): class _bitfield(Structure): _fields_ = [ - ("lock", c_uint32, 32), + ("pid2", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_lock(self, value): self.bits.lock = value - def get_lock(self): value = self.bits.lock; return value + def set_pid2(self, value): self.bits.pid2 = value + def get_pid2(self): value = self.bits.pid2; return value -class regioncfg_r(Union): +class pid3_r(Union): class _bitfield(Structure): _fields_ = [ - ("region0", c_uint32, 2), - ("region1", c_uint32, 2), - ("region2", c_uint32, 2), - ("region3", c_uint32, 2), - ("region4", c_uint32, 2), - ("region5", c_uint32, 2), - ("region6", c_uint32, 2), - ("region7", c_uint32, 2), - ("reserved0", c_uint32, 16), + ("pid3", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_region0(self, value): self.bits.region0 = value - def get_region0(self): value = self.bits.region0; return value - def set_region1(self, value): self.bits.region1 = value - def get_region1(self): value = self.bits.region1; return value - def set_region2(self, value): self.bits.region2 = value - def get_region2(self): value = self.bits.region2; return value - def set_region3(self, value): self.bits.region3 = value - def get_region3(self): value = self.bits.region3; return value - def set_region4(self, value): self.bits.region4 = value - def get_region4(self): value = self.bits.region4; return value - def set_region5(self, value): self.bits.region5 = value - def get_region5(self): value = self.bits.region5; return value - def set_region6(self, value): self.bits.region6 = value - def get_region6(self): value = self.bits.region6; return value - def set_region7(self, value): self.bits.region7 = value - def get_region7(self): value = self.bits.region7; return value + def set_pid3(self, value): self.bits.pid3 = value + def get_pid3(self): value = self.bits.pid3; return value -class axi_limit0_r(Union): +class cid0_r(Union): class _bitfield(Structure): _fields_ = [ - ("max_beats", c_uint32, 2), - ("reserved0", c_uint32, 2), - ("memtype", c_uint32, 4), - ("reserved1", c_uint32, 8), - ("max_outstanding_read_m1", c_uint32, 8), - ("max_outstanding_write_m1", c_uint32, 8), + ("cid0", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_max_beats(self, value): self.bits.max_beats = value - def get_max_beats(self): value = self.bits.max_beats; return value - def set_memtype(self, value): self.bits.memtype = value - def get_memtype(self): value = self.bits.memtype; return value - def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value - def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value - def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value - def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value + def set_cid0(self, value): self.bits.cid0 = value + def get_cid0(self): value = self.bits.cid0; return value -class axi_limit1_r(Union): +class cid1_r(Union): class _bitfield(Structure): _fields_ = [ - ("max_beats", c_uint32, 2), - ("reserved0", c_uint32, 2), - ("memtype", c_uint32, 4), - ("reserved1", c_uint32, 8), - ("max_outstanding_read_m1", c_uint32, 8), - ("max_outstanding_write_m1", c_uint32, 8), + ("cid1", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_max_beats(self, value): self.bits.max_beats = value - def get_max_beats(self): value = self.bits.max_beats; return value - def set_memtype(self, value): self.bits.memtype = value - def get_memtype(self): value = self.bits.memtype; return value - def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value - def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value - def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value - def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value + def set_cid1(self, value): self.bits.cid1 = value + def get_cid1(self): value = self.bits.cid1; return value -class axi_limit2_r(Union): +class cid2_r(Union): class _bitfield(Structure): _fields_ = [ - ("max_beats", c_uint32, 2), - ("reserved0", c_uint32, 2), - ("memtype", c_uint32, 4), - ("reserved1", c_uint32, 8), - ("max_outstanding_read_m1", c_uint32, 8), - ("max_outstanding_write_m1", c_uint32, 8), + ("cid2", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_max_beats(self, value): self.bits.max_beats = value - def get_max_beats(self): value = self.bits.max_beats; return value - def set_memtype(self, value): self.bits.memtype = value - def get_memtype(self): value = self.bits.memtype; return value - def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value - def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value - def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value - def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value + def set_cid2(self, value): self.bits.cid2 = value + def get_cid2(self): value = self.bits.cid2; return value -class axi_limit3_r(Union): +class cid3_r(Union): class _bitfield(Structure): _fields_ = [ - ("max_beats", c_uint32, 2), - ("reserved0", c_uint32, 2), - ("memtype", c_uint32, 4), - ("reserved1", c_uint32, 8), - ("max_outstanding_read_m1", c_uint32, 8), - ("max_outstanding_write_m1", c_uint32, 8), + ("cid3", c_uint32, 32), ] _fields_ = [("bits", _bitfield), ("word", c_uint32)] - def set_max_beats(self, value): self.bits.max_beats = value - def get_max_beats(self): value = self.bits.max_beats; return value - def set_memtype(self, value): self.bits.memtype = value - def get_memtype(self): value = self.bits.memtype; return value - def set_max_outstanding_read_m1(self, value): self.bits.max_outstanding_read_m1 = value - def get_max_outstanding_read_m1(self): value = self.bits.max_outstanding_read_m1; return value - def set_max_outstanding_write_m1(self, value): self.bits.max_outstanding_write_m1 = value - def get_max_outstanding_write_m1(self): value = self.bits.max_outstanding_write_m1; return value + def set_cid3(self, value): self.bits.cid3 = value + def get_cid3(self): value = self.bits.cid3; return value class pmcr_r(Union): -- cgit v1.2.1