From f842b69d007e70d70fc5cef3b6f1f50b4cabbd90 Mon Sep 17 00:00:00 2001 From: Diqing Zhong Date: Fri, 11 Dec 2020 13:07:37 +0100 Subject: MLBEDSW-3465: Add memory settings into sys config Signed-off-by: Diqing Zhong Change-Id: I4a5c53d0c5957595fc639b174b2b227ea043d409 --- ethosu/vela/tensor.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'ethosu/vela/tensor.py') diff --git a/ethosu/vela/tensor.py b/ethosu/vela/tensor.py index de97710a..257cb5ff 100644 --- a/ethosu/vela/tensor.py +++ b/ethosu/vela/tensor.py @@ -19,6 +19,7 @@ import copy import enum import uuid from collections import defaultdict +from enum import auto from functools import lru_cache from typing import Dict from typing import List @@ -62,6 +63,22 @@ class MemType(enum.IntFlag): return self.name +class BandwidthDirection(enum.IntEnum): + Read = 0 + Write = auto() + Size = auto() + + def display_name(self): + return self.name + + def identifier_name(self): + return self.name.lower() + + @staticmethod + def all(): + return (BandwidthDirection.Read, BandwidthDirection.Write) + + class MemArea(enum.IntFlag): Unknown = 0 Sram = 1 -- cgit v1.2.1