From d775e37669061824b1e7b9976611cf8cd1d0cf9e Mon Sep 17 00:00:00 2001 From: Tim Hall Date: Fri, 28 Aug 2020 18:33:38 +0100 Subject: MLBEDSW-2900: softmax output diff on FPGA - Corrected the rounding mode for softmax Signed-off-by: Tim Hall Change-Id: If136491c7668e85fba1e2c56c8cff11aa32db328 --- ethosu/vela/register_command_stream_generator.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'ethosu/vela/register_command_stream_generator.py') diff --git a/ethosu/vela/register_command_stream_generator.py b/ethosu/vela/register_command_stream_generator.py index 12ade8da..0a356475 100644 --- a/ethosu/vela/register_command_stream_generator.py +++ b/ethosu/vela/register_command_stream_generator.py @@ -436,7 +436,9 @@ def generate_register_command_stream(nng, sg, arch, verbose=False): # Specifies if global scale from the NPU_SET_OFM_SCALE register should be used instead of per-channel scale use_global_scale = False # Specifies type of rounding to be used. - rounding_mode = rounding.TFL + rounding_mode = ( + rounding.NATURAL if primary_op.attrs.get("rounding_mode", "") == b"NATURAL" else rounding.TFL + ) if primary_op.type == "ResizeBilinear": rounding_mode = rounding.TRUNCATE fmf = primary_op.attrs.get("fused_memory_function", None) -- cgit v1.2.1